AD9781 clock driver

I'm in the initial stages of bringing up an AD9781 circuit. I mistakenly used Fig. 59 from the data sheet to drive CLKP/N from an FPGA LVDS signal, which doesn't have enough differential swing to meet the AD9781 spec. This may be why I can't see anything change on the outputs (even though I can access SPI just fine, and the FPGA is getting a good DCO signal back). Strangely, I can ramp through SMP delay values (0-31) and at SMP=23 I see SEEK flipping from 0 to 1, which made me think there is an internal CLK signal after all. (I thought for some initial close-to-DC testing I could ignore the timing table stuff.)

Since most people probably drive the CLKP/N pins from an FPGA, do you have a recommended LVDS-LVPECL translator or suitable circuit? The MAX9375 seems like it will work, but it's pretty expensive.

Thanks for any info.