I'm in the initial stages of bringing up an AD9781 circuit. I mistakenly used Fig. 59 from the data sheet to drive CLKP/N from an FPGA LVDS signal, which doesn't have enough differential swing to meet the AD9781 spec. This may be why I can't see anything change on the outputs (even though I can access SPI just fine, and the FPGA is getting a good DCO signal back). Strangely, I can ramp through SMP delay values (0-31) and at SMP=23 I see SEEK flipping from 0 to 1, which made me think there is an internal CLK signal after all. (I thought for some initial close-to-DC testing I could ignore the timing table stuff.)
Since most people probably drive the CLKP/N pins from an FPGA, do you have a recommended LVDS-LVPECL translator or suitable circuit? The MAX9375 seems like it will work, but it's pretty expensive.
Thanks for any info.
Thanks for reaching out.
Can you provide a scope shot of the FPGA clock? The CLK input of AD9781 has to be centered on a common-mode voltage of 400mv with an acceptable range of 300mv to 500mv. Each input pin can safely swing from 200 mV p-p to 1 V p-p of the common-mode.
I suggest taking a look at the ADCLK905 PECL buffer.
Hi,The part that Mark suggested is the one used in the evaluation board of the device family.Please see schematic in this link:https://wiki.analog.com/resources/eval/dpg/eval-ad9783Best regards,Shine
Thanks for the replies. It's not clear to me that the ADCLK905 will work with LVDS inputs, the data sheet makes no mention of it other than saying there's a center-tapped 100 ohm resistor on the inputs.
LVDS signals can be treated using Fig. 28 in datasheet (AC coupling differential signals). Add Bias to the Vref pin as necessary so that the max peak of the ac-coupled LVDS signal is within the minimum threshold of Vih (Vee + 1.6).