AD9106 example 3 does not work

Hi CJ,

Seems like you are not using our evaluation board.

Please pulse the RESET pin high-low-high before SPI communication. This will set register values to default.
In writing to the SPI registers, there is a sequence that should be followed. Please try writing 1 to registers 0x1E and 0x1D last.

Best regards,
Shine

Hi Shine,

It does not work either. I update the registers values with the example data and then set bits RAMUPDATE and RUN, as you suggest. Then I check the CFG_ERROR and everything seems ok. After that, I activate TRIGGER and nothing happens. Later, CFG_ERROR becomes 0xFFFF. Any idea? Thanks a lot.

C.J.

Hi CJ,

Can you send me your schematic?
Please compare your clock input to datasheet-recommended clock input.
Also, please check if your reference voltage is 1V.

What supply voltage are you using?

Best regards,
Shine

Hi Shine,

I attach the schematic sheet. All power pins are connected to 3V3 rails. We use the internal voltage reference, so C141 is added for decoupling. We also use the auto calibration functionality, so FSADJ1 and CAL_SENSE are connected together. Moreover, a resistor is included from those pin to GND. R22 is 4K and R21 is a 10K potentiometer. This should allow is to adjust the Rcal_sense value between 4K and 14K, so Iout should be 2mA and 8mA. Now R21 is calibrated to provide 4mA.

RESET pin is always at 3v3 because design constraints. We use RESET software or power down and up the entire board if a full reset is required. Clock input is 180MHz. SPI interface (SCLK) works at 20MHz.

Any help is very welcome.

C.J.

PDF

Hi CJ,

Please check the following:

1. Outputs of DLDO1, DLDO2, CLDO should be 1.8V. And these pins should be bypassed with 0.1uF capacitors when operating the device at 3.3V.

2. REFIO output voltage or voltage across C141 and AGND should be 1V.

3. What is R13 value? And what equipment are you using as clock source? What is the clock signal amplitude? Should be at least 150mV peak-to-peak.

4. Probe the SPI waveforms using an oscilloscope to check timing. Data should be valid at SCLK rising edge.

Best regards,
Shine

Hi Shine,

We have checked all the points you mentioned:

-Outputs of DLDO1, DLDO2, CLDO are 1.8V
-Voltage across C141 is exactly 1V.
-R13 is 100 ohms. We use a 180MHz quartz oscillator as clock reference, and then a CDCLVP1204 high performance clock buffer connected to the AD9106's clock input. Differential output peak-to-peak voltage is 1.2volts. I attach the schematic sheet, just in case.
-SPI works well. We are able to write and read back the content of all readable registers (including the 4K SRAM), so it does not seem to be the problem.

No idea about what is wrong.
C.J.

PDF

Hi CJ,

I hope you have a spectrum analyzer to check if there is clock leakage out of the DAC channels.
Even though you are not generating a waveform, when you connect a DAC channel to a spectrum analyzer, you should be able to see a small signal amplitude at the clock frequency.
If there is none, I suggest you try to remove the 100-Ohm resistor, R13, as it may be loading the clock source.

Finally, I'm sharing with you my pseudocode with which you can compare your code.

1. Set initial values of IOs.
   • RESET - logic high
   • TRIGGER - logic high
   • CS - logic high
2. Set SPI frequency and mode.
   • Clock is logic low when idle or leads with a rising edge and trails with a falling edge.
   • Data should be held high during the clock rising edge and before the clock falling edge.
3. Pulse RESET to logic low then high to reset register values.
4. Proceed with register read or write. (pages 22-23 of datasheet)
   1. If loading a pattern from SRAM, write data on SRAM registers first. (page 27 of datasheet)
      1. To write data: Enable MEM_ACCESS bit in 0x1E register. Write left-justified (15:4) data to SRAM registers, 0x6000 to 0x6FFF. Disable MEM_ACCESS bit.
      2. To read data: Enable BUF_READ and MEM_ACCESS bits in 0x1E register. After reading data from SRAM registers, disable BUF_READ and MEM_ACCESS bits.
   2. Write on SPI registers. Update last bits of registers 0x1E (RUN bit) and 0x1D (RAMUPDATE bit) at the end of the write sequence.

Best regards,
Shine

Hi CJ,
Were you able to solve your problem? I have the same problem!

Hi,

No, not at all. Finally, I decided to purchase an AD9106-EBZ demo-board to check the code with it. I am still waiting for the delivery.

Best,
C.J.

Thanks for your response!

If you were able to solve the problem or were changed the condition of your circuit.
Please inform us by updating this post.

Best Regard
- Pourya