Post Go back to editing

EVAL-AD9746: data clock generation


I use EVAL-AD9746 + AD-DAC-FMC-ADP + SDP-H1.

I can't generate a vector (single tone as shown as example within UG-1624), because of the error message: "No data clock was detected"  

On EVAL-AD9746, the PLL of AD9516, seems to be unlocked. 

In my test setup, a sinusoidal 100 MHz is generated at J1 input (from R&S SMF 100A). 

U5 VCXO is not mounted on the board. REFIN2 is not connected.  

A 50 MHz is generated at J2 input from a signal generator (REFIN1).

Could help me to investigate on this ?

Thanks and regards,