EVAL-AD9746: data clock generation

Hello,

I use EVAL-AD9746 + AD-DAC-FMC-ADP + SDP-H1.

I can't generate a vector (single tone as shown as example within UG-1624), because of the error message: "No data clock was detected"  

On EVAL-AD9746, the PLL of AD9516, seems to be unlocked. 

In my test setup, a sinusoidal 100 MHz is generated at J1 input (from R&S SMF 100A). 

U5 VCXO is not mounted on the board. REFIN2 is not connected.  

A 50 MHz is generated at J2 input from a signal generator (REFIN1).

Could help me to investigate on this ?

Thanks and regards,

Pierre BRIOTTET

  • 0
    •  Analog Employees 
    on Sep 9, 2020 6:45 AM 2 months ago

    Hi Pierre,

    The AD9516 has two options for its clock source to be distributed to the DAC, one is direct thru the CLK pins (routed to J1 at AD9747 evalboard), or either a second option is thru the output of the on-chip PLL/VCO using the REFINx pins (routed to J2). 

    For the AD9747 evalboard, it uses option one for the clock source (100MHz at J1). You should not connect a clock source to the REFINx pins since you already have the 100MHz at CLK pins of AD9516. Also, make sure to write 0b01 to address 0x1e1 using the SPI software and bypass the dividers, as discussed on the UG-1624. This will ensure that the input at the CLK pins will be the one to be distributed.

    Regards,

    Mark

  • Thanks a lot for your help.

    Actually, I modified the board configuration in order to generate DAC clock thanks to J4 SMA input connector. 

    My issue is still not resolved, the SDP-H1 does not detect Data Clock Output, so I am not able to launch a test scenario on DPGdownloaderlite.

    I measured DCO at DAC output and the signal is present on J3 when modify the position JP16. But when setting back JP16 to supply SDP-H1 with DCO signal, this signal is not detected.

    Could you please help me on this topic?

    Thanks again for your help.

    Regards,

    PierreB  

  • 0
    •  Analog Employees 
    on Sep 10, 2020 11:06 AM 2 months ago in reply to PierreB

    Hi PierreB,

    Can you upload a photo of the clock signal you're getting at J3? What amplitude are you getting? Do you also observe the same signal when you probe to pin 4 and pin 3 of U13 when JP16 is back to the original position?

    You can also try shorting JP25 and see what happens.

    Regards,

    Mark

  • Hello,

    Thanks again.

    You will find in attachment the signal measured at J3. 

    I encounter probe issues to measure cleanly the signal at U13 output. The measured signal is very noisy.

    I will try again with another probe and will provide it to you.

    Could you tell what are the mandatory caracteristics of the signal at U13 input/output?

    For information, JP25 is shorted by default.

    Regards,

    PierreB

  • 0
    •  Analog Employees 
    on Sep 14, 2020 9:09 AM 2 months ago in reply to PierreB

    Hi Pierre,

    Thanks for the scope shot. For U13 input, you should expect a similar waveform you're observing at J3 output. For its output. you should expect a low voltage differential signal (LVDS) clock that has an offset at ~1.25V with peaks at ~1.5V and ~1V. So the "noise" that you're observing is maybe actually the signal as expected. The same goes for U14.

    Have you tried to remove the JP25 short?

    Regards,

    Mark