Hi I am working with a FPGA-DAC modulator system. FPGA in use is Arria10, JESD clock system consists ADF4355 as clock source, with hmc862 and ad9508 as divider.
AD9163 is running at 6Gsps, with 8x interpol. Lane rate is 3750mbps.
L=8, M=2, F=1, K=32, with NCO enabled.
there is a 1% to 0.5% chance the ad9163 outputs wierd spectrum after reconfig.
When it is good:
when its bad:
Image will be generated at +/- 375MHz position(1/2 of my output sample rate).
Reconfig flow is:
Set 4355, set 9508, wait 4355 to lock, set 9163, recal fpga transciever and pll, bring up link. During the adnormal scenario, syncn is high, ad9163 register 0x470 471 472 473 all reads out 0xFF.
Could anyone help with this problem? Many thanks
