Post Go back to editing

8 PCS AD9175 Synchronization clock design

Dear ADI colleague,

I'm DFAE from ESPL, our customer will design a multi-channel digital process system which include 8 x ADC + 8 x AD9172,  ADC and DAC need synchronously working, the specific parameters of DAC as following:

1. 4 x AD9172 every board, 2 boards for the DAC channel, all the DAC need synchronization;

2. DAC output frequency range is 1300MHz ~ 2400MHz,  AD9175 will work in Mode

customer design sample rate will be 2.5GSPS, after x 4, the CLKIN+/CLKIN- will up to 10GHz (will not used AD9175 internal PLL for drift by temperature), so customer need design a 10GHz synchronization clock source board for 8PCS AD9172;

3. We have recommended the following synchronization clock source design: 10GHz clock source --> PA --> 1:4 Power Divider --> 4 CH 10GHz clock output 

4. Customer has confirmed the following JESD204B Technical Article documents, they were not sure if our recommended clock soure solution can match JESD204 synchronization requirement and have the following question:

   a. Which subclass belong to Subclass 1 and Subclass 2 for customer's design?

   b. How about the length of DCLK and SYSREF PCB line for single AD9175?

   c. What requirement are the DCLK or SYSREF clock for Multiple AD9175?

5. Can we used AD9175 internal PLL for multiple AD9175 synchronization DAC system? if we can't, could you recommend the 8 PCS AD9175 synchronization clock soure solution?

Thanks a lot!

Parents Reply Children
No Data