I have a question with regards REFCLK specification.
We are using REFCLK of 112MHz and we are generating this from clock source that stabilizes to ±5×10^-6(±5ppm) after 2 min of power-up.
And we are setting the DAC before 2 min and we are not able to see any output . But when we send the DAC setting once again we are able to see the output.
When there is no output, there is no problem with PLL_LOCK.
Please let me know if there is any detailed specification for REFCLK
With best regards