[AD9102] Clock LDO Output inactive


I try to communicate with an AD9102 via SPI but get no answer yet. The Chip is running at 3.3V for all VDDs, I can see the DLDO1 Output = 1.8V, RESET Pin gets pulled up to VDD if left floating and I find the REFIO around 1V therefore the Chip is alive.

But the CLDO - Clock Power Supply Output - by the internal regulator (should be enabled by default / after reset?!) stays at Ground Voltage Level. As a result the AC coupled differential clock at CLKP/CLKN pins is LVDS around Ground Level Voltage. According to https://ez.analog.com/data_converters/high-speed_dacs/f/q-a/22861/ad9102-no-spi-response CLKP & CLKN should be self biased on chip to around 0.9V, which I think is the reason for the SPI communication not working.

The CLDO Pin is connected to a 100nF bypass Capacitor, CLKP & CLKN Input is AC-coupled LVDS Clock @ 1MHz (adjustable).

EDIT: I've checked the Voltages on several device pins with a tiny probe needle to look for cold solder joints. The device CLKVDD pin is supplied with the desired +3.3V, CLDO pin is at Ground Level. I'm assuming the chips Clock domain to be dead. I might try to remove the Chip and mount a new one...

If someone got other advises I'm happy to hear them.

Thanks in advance

Pin Voltage Check
[edited by: Lauri at 9:13 AM (GMT 0) on 7 Aug 2020]