Data interface

There is different options for data interface for an High Speed DAC: CMOS, LVDS or JESD204A. Which one should I choose and why? 

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  • CMOS interface is the simpliest to use as the interface is single ended but it is limited in speed to roughly 250MHz hence limiting the Data rate update.

    LVDS is a differential interface that can run much faster but uses double the number of wires vs. CMOS. It is the most common and recommended interface when data update rate is > 300Msps. As data interface speed increases above 1GHz, the timing of an LVDS parrallel interface becomes more difficult to achieve as tolerance for inter-lane skew is small.

    Finally, JESD204A is a serial interface where clock phase is recovered from the data stream. It is defined by a standard (for standard please go here) where max speed is set to 3.125Gbps. As the interface uses a 8B/10B encoding (http://standards.ieee.org/getieee802/), each JESD204A lane has a maximum speed of 312.5Mbyte/s.AS JESD204A recover the clock phase, there is no interlane skew requirement which ease greatly the interconnection. JESD204A is emerging as an option for high speed converters as it reduces the number of connections and ease timing between parts.)

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