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I'm considering using two AD9734 DACs for I/Q modulation.  Througout the datasheet, much is made of using DATACLK_OUT to generate DATACLK_IN.  For example, on page 35 the data sheet says, "Using the DATACLK_OUT signal to generate the data allows most of the internal process, temperature, and voltage delay variation to be cancelled."

Since the incoming LVDS data is sampled with DATACLK_IN, and transferred via FIFO to the DACCLK domain, I don't see why this is so important.  Everything should be OK if I guarantee that DATACLK_IN is frequency locked to DACCLK, especially if I use the LVDS Controller in AUTO mode to maintain a good phase on the Data Sampling Signal (DSS).

We do intend to use the DAC's internal FIFO even though we will have both an I DAC and a Q DAC.  At startup, we plan to feed the DAC outputs back to our FPGA through ADCs and run an algorithm to align them.

Does Analog Devices agree that I can avoid using DATACLK_OUT in this system?  The main reason I want to avoid it is that I have two DACS, and therefore two DATACLK_OUTs, but I want to clock the entire I/Q LVDS bus with a single clock.