AD9735 LVDS input voltage range

The input voltage range on the digital LVDS inputs of the AD9735 DAC is specified to be 825 mV min to 1575 mV max.  The absolute maximum voltage rating for these inputs is 3.6 V (DVDD33 + 0.3V).

We plan to drive these inputs from an FPGA with DC coupling.  Based on the published characteristics of the FPGA LVDS driver, it seems that it will output a voltage between 825 mV and 1675 mV.

Will the 1675 mV, which is greater than the AD9735's "max" value of 1575 mV, be a problem?

Thanks,

Keith

  • 0
    •  Analog Employees 
    on Oct 15, 2011 12:30 AM

    The AD9734/AD9735/AD9736 LVDS receivers are compliant to IEEE Std. 1596.3-1996. The 1675 mV driver exceeds the data sheet limits, as well as the driver limits in the 1596 standard, and so the guarantees and reliability associated with the data sheet limits would not apply to that application. Generally, we do not recommend operating the devices outside their data sheet limits.

  • 0
    •  Analog Employees 
    on Aug 2, 2018 4:27 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin