The input voltage range on the digital LVDS inputs of the AD9735 DAC is specified to be 825 mV min to 1575 mV max. The absolute maximum voltage rating for these inputs is 3.6 V (DVDD33 + 0.3V).
We plan to drive these inputs from an FPGA with DC coupling. Based on the published characteristics of the FPGA LVDS driver, it seems that it will output a voltage between 825 mV and 1675 mV.
Will the 1675 mV, which is greater than the AD9735's "max" value of 1575 mV, be a problem?
The AD9734/AD9735/AD9736 LVDS receivers are compliant to IEEE Std. 1596.3-1996. The 1675 mV driver exceeds the data sheet limits, as well as the driver limits in the 1596 standard, and so the guarantees and reliability associated with the data sheet limits would not apply to that application. Generally, we do not recommend operating the devices outside their data sheet limits.