Good day everyone.
I just wanted to explain to you guys what i's happening in my design. Here are the features:
- FPGA wired to the DAC in order to produce signals up to 1 GHz (not necessarily tones, but more complex signals).
- DAC clocked with a 2100 MHz stable syntethiser.
- Generation of samples issued to the DAC duly tested (hence correct).
- Configuration issued to the DAC according to the "recommended start-up sequence" provided on the datasheet.
And these are the facts:
- The generated signal on the SA always appears with a mirror signal at 1/4 the Fdac (525 MHz), besides of the obvious 1/2 Fdac image (see image "mirrored.jpg").
- After many tries, I've discovered empirically that by performing a power down (bit 0 of register 0x01), some times, the 1/4 Fdac image disappears showing the right signal (see image "correct.jpg").
I've tried to read back all the registers in order to find a difference that explains this fact, but unsuccessfuly (in both cases, the essential registers show the same values).
And finally, even if it seems strange, I've realised that when the DAC hasn't been used for some time (it's "cold"), the signal obtained after power-downing the IC is less likely to be correct than whe the DAC is "hot".
Anyone feels that can help?
Every comment will be welcomed.