DCI Delay change in AD9148


I'm using AD9148 in single port mode, two's complement binary data input format.

With one DAC output, when producing digital sine wave to inputs, I can see a small glitch at dac outputs which looks to be a possible data timing error.

I was trying to play with the DCI Delay register setting to see I it is possible to get rid of it. However, there was no effect due to the DCI Delay setting (Register 0x72) in Rev.A datasheet.

I wonder if the DCI Delay register (0x72) is actually located at address 0x72?

Always, no matter the value written to it, the read back returns 0x00 from address 0x72.

Other registers, e.g. 0x74 (LVDS pad ctrl) I can write and read the same value back.

Any suggestions?