We are using AD high speed DAC AD9746 on one of our board.
The DAC is configured in single port mode with data coming from a FPGA. We are
seeing some issues with clocking data into the DAC. From the datasheet it was
not clear when the data will be sampled but we assumed that will occur both on
positive and negative edge of DAC CLK. We got it working but not reliably – we
have to power-up few times.
Is there any document explaining the initialization sequence in details?
Also, does the DAC clock should be present before the Reset is asserted?
How about the status of the SPI pins? What is the exact sequence that reset the
DAC after the power up?
Your help will be highly appreciated.