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AD9746 High Speed DAC issue?

Dear Sirs,

 

We are using AD high speed DAC AD9746 on one of our board.
The DAC is configured in single port mode with data coming from a FPGA. We are
seeing some issues with clocking data into the DAC. From the datasheet it was
not clear when the data will be sampled but we assumed that will occur both on
positive and negative edge of DAC CLK. We got it working but not reliably – we

have to power-up few times.

Is there any document explaining the initialization sequence in details?

Also, does the DAC clock should be present before the Reset is asserted?
How about the status of the SPI pins? What is the exact sequence that reset the
DAC after the power up?

 

Your help will be highly appreciated.

 

Regards,

Dan

  • From the datasheet it was

    not clear when the data will be sampled but we assumed that will occur both on

    positive and negative edge of DAC CLK. We got it working but not reliably – we 

    have to power-up few times

    The Figure 28 of the data sheet shows the interface timing for Single port mode and the data is clocked in

    on both the rising and falling edges of DAC CLK. As mentioned in the data sheet the DCO signal which

    is a output that is delayed DACCLK can be used as a reference signal to time the data if needed.

    There was no wrriteup on the intitinalization of the part because the part has very few SPI registers

    and it was felt should be straight forward to initialize. If you have a qquestion on the order of

    setting the registers let us know.

    Also, does the DAC clock should be present before the Reset is asserted? No the DAC Clock is not

    required for a RESET assertion.


    How about the status of the SPI pins?  Reset asserted sets the register to default values at start up

    What is the exact sequence that reset the
    DAC after the power up?

     

    When the AD9746 is powered up, an active high pulse applied to the RESET pin should follow. This insures the default state of all control register bits.  Then you should program the registers for values different then the default

    for features you want to use.