AD9764
Production
The AD9764 is the 14-bit resolution member of the TxDAC®
series of high performance, low power CMOS digital-to-analog
converters (DACs). The TxDAC®; family...
Datasheet
AD9764 on Analog.com
AD6644
Production
The AD6644 is a high speed, high performance, monolithic 14-bit analog-to-digital converter (ADC). All necessary functions, including track-and-hold (TH...
Datasheet
AD6644 on Analog.com
AD9631
Production
The AD9631/AD9632 are very high speed and wide bandwidth amplifiers. The AD9631 is unity gain stable. The AD9632 is stable at gains of 2 or greater. Using...
Datasheet
AD9631 on Analog.com
Hi
I have designed a DAQ borad including AD9764, AD6644 and it communicates with Xilinx Spartan 3AN FPGA through FX2 expansion connector.
As indicated in the attachments we can see the input&output connections and the clock signal (which is RC filtered version of Clockin at 16MHz coming from the FPGA) . I am wondering why i am getting the same voltages at the IOUTA and OUTB nodes at the AD9764 output (simply 0 or 20mV at the output of AD9631 opamp ) although I apply the code "00000001111111" from the FPGA. I checked the DAC inputs and see that they are as the FPGA output. Is it about the AD9764 or the AD9631 opamp or the noise level?
I will appreciate any help .
Thank you very much
HIDIR
Hi
In the AN-420 application note about using the AD9764-EB Evaluation Board it is suggested to use C12,C13=22 pF and R20,R38=50 Ohm (as can be seen from the attached image).
It is also said that :
" OUTPUT CONFIGURATIONS
Resistive Load
The single-ended outputs of the AD9708/AD9760/AD9762/ AD9764 may be observed through J3 and J4. At these points the user will observe IOUTA and its complement, output IOUTB (respectively). The output voltage is developed by the flow of output current into 50 Ohm resistors
(R20, R38) and 20 pF capacitors (C12, C13). One RC net is shunted to ground for each output. "
Is it the cause of my problem ?
Hi
In the AN-420 application note about using the AD9764-EB Evaluation Board it is suggested to use C12,C13=22 pF and R20,R38=50 Ohm (as can be seen from the attached image).
It is also said that :
" OUTPUT CONFIGURATIONS
Resistive Load
The single-ended outputs of the AD9708/AD9760/AD9762/ AD9764 may be observed through J3 and J4. At these points the user will observe IOUTA and its complement, output IOUTB (respectively). The output voltage is developed by the flow of output current into 50 Ohm resistors
(R20, R38) and 20 pF capacitors (C12, C13). One RC net is shunted to ground for each output. "
Is it the cause of my problem ?
