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AD9764 output

Hi

I have designed a DAQ borad including AD9764, AD6644 and it communicates with Xilinx Spartan 3AN FPGA through FX2 expansion connector.

As indicated in the attachments we can see the input&output connections and the clock signal (which is RC filtered version of Clockin at 16MHz coming from the FPGA) . I am wondering why i am getting the same voltages at the IOUTA and OUTB nodes at the AD9764 output (simply 0 or 20mV at the output of AD9631 opamp ) although I apply the code "00000001111111" from the FPGA. I checked the DAC inputs and see that they are as the FPGA output.  Is it about the AD9764 or the AD9631 opamp or the noise level?

I will appreciate any help .

Thank you very much

HIDIR

attachments.zip
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  • Applying   

         "11111111111111" to the DAC input

              I have V_IOUTA=2.8V=V_IOUTB, the voltage at the OPMAP input is 1.4V, the current from the 3.3VD supply sources 29mA

         "00000001111111"

              I have V_IOUTA=2.8V=V_IOUTB, the voltage at the OPMAP input is 1.4V, the current from the 3.3VD supply sources 70mA

         "00000000000000"

              I have V_IOUTA=2.8V=V_IOUTB, the voltage at the OPMAP input is 1.4V, the current from the 3.3VD supply sources 113mA .

    Did I reach the breakdown limit of the AD9764 ?

    Thank you

Reply
  • Applying   

         "11111111111111" to the DAC input

              I have V_IOUTA=2.8V=V_IOUTB, the voltage at the OPMAP input is 1.4V, the current from the 3.3VD supply sources 29mA

         "00000001111111"

              I have V_IOUTA=2.8V=V_IOUTB, the voltage at the OPMAP input is 1.4V, the current from the 3.3VD supply sources 70mA

         "00000000000000"

              I have V_IOUTA=2.8V=V_IOUTB, the voltage at the OPMAP input is 1.4V, the current from the 3.3VD supply sources 113mA .

    Did I reach the breakdown limit of the AD9764 ?

    Thank you

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