AD9764 output

Applying   

     "11111111111111" to the DAC input

          I have V_IOUTA=2.8V=V_IOUTB, the voltage at the OPMAP input is 1.4V, the current from the 3.3VD supply sources 29mA

     "00000001111111"

          I have V_IOUTA=2.8V=V_IOUTB, the voltage at the OPMAP input is 1.4V, the current from the 3.3VD supply sources 70mA

     "00000000000000"

          I have V_IOUTA=2.8V=V_IOUTB, the voltage at the OPMAP input is 1.4V, the current from the 3.3VD supply sources 113mA .

Did I reach the breakdown limit of the AD9764 ?

Thank you

Thank you AndyR

Hi-

I moved this question about the AD9764 to the High-Speed DACs Community.  Someone here should be able to assist you.

Regards,

AndyR

EngineerZone Community Manager

Hi

In the AN-420 application note about using the AD9764-EB Evaluation Board it is suggested to use C12,C13=22 pF and R20,R38=50 Ohm (as can be seen from the attached image).

It is also said that :

" OUTPUT CONFIGURATIONS

Resistive Load

The single-ended outputs of the AD9708/AD9760/AD9762/ AD9764 may be observed through J3 and J4. At these points the user will observe IOUTA and its complement, output IOUTB (respectively). The output voltage is developed by the flow of output current into 50 Ohm resistors

(R20, R38) and 20 pF capacitors (C12, C13). One RC net is shunted to ground for each output. "

Is it the cause of my problem ?

Hi

I have connected the suggested components R20, R38,C12, C13.

Now I observe (with the DC coupled channel of the oscilloscope)

V_IOUTA=900mV and V_IOUTB=12mV with 120 and 4 mVpk-pk .The voltage at the OPMAP inputs are 3 and 7 mV respectively. The opamp output is -845 mV .

The 3.3VD supply sources 29mA, 74 mA and 112mA for the DAC codewords of      "00000000000000",   "00000001111111" and "11111111111111" respectively.

I could not see difference in the output .

Any help about how to carry the DAC output test steps  or the problem I face ..

Thank you

Is it about the AVCC=5V supply ,that it needs to supply more current to the AD9764 output; that is why i see weak signals at the output ?

Hi Mr. Larry Welchusa

Thank you very much for your help

I attached the schematic pdf file. I can also send the layout files' pictures.

In addition to the schematic i have made two differences in the layout. The first one is adding two capacitors for obtaining CLOCK signal from the incoming CLOCKIN signal (i added 100nF capacitors in serial with the AD9764 and 74LCX574(D flip flop at the AD6644 output) clock inputs ). Thus the 98th pin of the Hirose FX2 connector is then CLOCKIN. http://ez.analog.com/servlet/JiveServlet/download/59065-11376/AD9764clock.jpg

The second is the addition of RC parallel pairs at the AD9764 IOUT pins . ez.analog.com/.../DiffAmpConfig.JPG

Also i do not think that there is a current sourcing lack in the supplies . The AVCC=5V and it sources 315 mA (6.5V and 350mA limited by the Agilent DC power supply). The DVDD=3.3V sources 116mA (for all high input of AD9764) and it is 5.5V and 150mA limited. The AVEE=-5V sources 20 to 40 mA (only for the OPAMPs) and 8V and 100mA limited. The Vref=2.4V (only for the AD6644 and AD8138) and limited to 4.4V and 100mA (sources no current when the AVCC is connected).

I use Tektronix oscilloscope to observe the signals. I use Xilinx SPARTAN 3AN FPGA kit (the connection to the DAQ card is established using Hirose FX2 connector).

Thank you very much.

Hi HIDIR -

Would it be possible for you to send us your complete schematic for review?

Thanks,

Larry

I have already added 50 ohm resistors in parallel with 22pF capacitors to ground in between IOUTA and R18 as well as between IOUTB and R19.

Hi HIDIR -

I recommend you add 25 ohm resistors to ground in between IOUTA and R18 as well as between IOUTB and R19. With 2K resistor R15 you set IOUTFS to 20ma. The voltage swing at !OUTA and IOUTB will then be 0 to .5 volts.

Thanks,

Larry