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AD9764 clock input and COMP2 voltage

Hi ,

I am feeding my AD9764 DAC using a 16 MHz clock generated by Xilinx Spartan3AN FPGA and the clock signal is a square wave with 800 mV mean and 1.36 Vpk-pk .

Also i see about 2 V in the COMP2 pin of AD9764 but i must see 0 V although i connect it to the ground using 0.1uF capacitor . I have checked the pins and the layout and could not find an answer ? What can be the cause of seeing 2V at COMP2?

AD9764 is not getting hot and i see about 500mV at the differential opamp output for a "00000000000000" input from FPGA . I am not sure if the DAC is working . Do you have any suggestion on how to test AD9764 in my situation using FPGA ?

How can I see the timing specifications of the clock on the TDS2022B oscilloscope ? (http://ez.analog.com/message/57999#57999)

Any help or suggestion about the testing, the clock signal or the wrong COMP2 voltage ?

thank you very much

  • Hi HIDIR -

    COMP2 is an internal DAC core bias node that you've bypassed to ground using a cap. This voltage should not be zero.

    I think your clock voltage swing is too small. If DVDD = +3V, you should have a 2.2V to 3V peak to peak swing between 0V and 2.2V or 3V. The Clock input will recognize this as a transition from logic 0 to logic 1.

    Thanks,

    Larry

  • Hi Mr. Larry

    I am getting the FPGA clock output sufficient enough to produce the cmos logic levels as you said 0 to 3.3 Vpp.

    Actually the clock output after connecting the card drops to 500 mV mean and 1Vpk-pk what should be the reason for that ? I will try to use the buffer NC7SZ32 to supply the required clock for AD6644 and AD9764.

    The schematic is as in http://ez.analog.com/servlet/JiveServlet/download/59561-11448/boardHIDIR.pdf

    Is it  the transformer needed to create the differential clock signals for the AD6644 cause the problem ?

    Thank you

  • Hi HIDIR -

    The AD9764 CLOCK input will draw at most +/- 10 micro-amps. You may be abae to connect an FPGA clock output directly to the AD9764 CLOCK input. If not, using the NC7SZ32 as a buffer is also a good idea.

    If you use the transformer circuit in your schematic I would suggest that you not AC couple pin 5 and pin 3. Connect XFMR pin 3 directly to AD9764 CLOCK input and connect XFMR pin 5 directly to ground. Inputs to the CLOCK terminal should be ground referenced.

    Thanks,

    Larry

  • Hi Mr. Larry,

    I have connected 100 Ohm resistor in series with the transformer input and disconnected the AC coupling capacitors as you suggested (but still looking forward for the experiment with the buffer, i could not get it yet) :

    Now I have disconnected the card from the FPGA and applied the input signals ; DC power supply signals  from Agilent 3648A, the AnalogIN (Utility-DC ON) and clock signals from the Agilent 33220A waveform generators. For the signal generators the  Utility-Output setup is  50 Ohm. Additionally i have taken the measurements using Tektronix TDS 2022B Oscilloscope and its CH1, CH2 are 10X and DC coupled.

    1) All the AD6644 power pins (AVCC=5V, GND, DVCC=3.3V, VREF=2.4V) are correct and C1,C2 has 1.35V mean, DNC has 240mV mean, DMID has 1.7V DC voltages.

    2)

    I have applied 16 MHz square wave signal with +1.7V DC offset and 3.7Vpk-pk, 50%duty cycle  from the signal generator.

    I have measured the ENC and ENCBAR (differential clock signals for AD6644) as in the figure below :

    3) The CLOCK signal (CH1) and the signal at the transformer input (CH2 which is also the clock signal input for the AD9764) are as indicated below :

    4) If the clock signals are correct I am trying to be sure if the ADC and DAC are working as expected or not.

    Starting for the AD6644 :

    I am using DC coupled input configuration

    Since VREF=2.4V DC, the input to the board is 0V (i have applied -60mV DC from the signal generator to obtain 0V DC at the opamp input VIN) resulting in AIN and AINBAR= 2.4 V as seen below :

    According to the AD6644 two's complement output coding table below

    i should have 00...0/11...1 coding at the output .

    Looking at the timing diagram

    if i am not wrong at the DRY signal's rising edge i should have the output coding as indicated above .

    For OVR=150 mV DC (no overflow) i have DRY (CH1),  ENC (CH2) plotted together as seen below:

      and DRY (CH2), D13(CH1) plotted together as seen below:

    How should i decide when i get D13= logic '0' ? Does it mean i do not understand the timing diagram or i have error in the card i have created ? If it is an error in the card i have just ordered the evaluation boards..

    Please any help or suggestion about the ENC signals, timing diagram, output coding and the outputs from my board .

    Thank you very much

    HIDIR

  • Hi HIDIR -

    I'll get back to you on this Monday.

    Thanks,

    Larry

  • Hi HIDIR -

    The ENC signal you show in the 4th scope capture form the top is not a valid waveform. It has multiple clock edges within each pulse that may or may not initiate an ADC conversion. ENC should always be shaped like the waveforms in the first scope capture.

    Setting the ADC input to 50% will put you in a place where all of the output bits will toggle. You'll go back and forth between all zero and all 1's.

    Thanks,

    Larry

  • Hi Mr. Larry -

    Thank you very much for your reply .

    Can I directly connect the FPGA clock signal output which is 6.6V pk-pk 1.75 Vmean 16 MHz square wave signal ? In the 4th page of AD6644 datasheet it is ENCODE inputs are 0.4V pk-pk differential input voltage and logic '0' voltage is 0.4V, logic '1' voltage is 2.5 V typically for 3.3V DVCC. In this case i will have 6.6/2+1.8=5V signal at the AD46644 ENC signal. Does it cause a damage to AD6644 ?

    I need to correct the ENC and ENCBAR as you mentioned above then take the same measurements .

    Thanks,

    HIDIR

  • Hi HIDIR -

    ENC and ENCBAR voltages cannot exceed the AVcc power supply voltage present on your board by more than 0.25V. The operating range for AVcc is 4.85 to 5.25V. If AVcc is 5v or more a 5V logic 1 level will work fine.

    If ENC and ENCBAR exceed AVCC you will get a latch up condition. Your system will stop working and you'll have to cycle the power. No damage will occur.

    Thanks,

    Larry

  • Hi Mr. Larry -

    I have disconnected the transformer and got the ENC, ENCBAR signals directly from the FPGA.

    Here is the ENC (CH1) and ENCBAR(CH2) at the AD6644 input :

    I want to learn if my understanding of the timing diagram OK or not. The 14 bit output data, DRY and OVR are sampled by the flip flop at the ADC output by the ENC signal. At each cycle i need to get the data at the rising edge of the ENC signal and when the data ready is logic '1', am I right ? Is there a different approach or algorithm i need to follow? Is the timing diagram for the max. sampling frequency and does it change for 16 MHz ?

    Thanks

    HIDIR

  • Hi HIDIR -

    Each rising edge of ENC/ENCBAR causes the ADC to start a conversion. Each sample output by the AD6644 on D[13:0] and OVR has a timing relationship with the DRY output signal such that the rising edge of DRY should be used to clock data into the input flip flops of your FPGA.

    The set up time (Ts) and hold time (Th) in figure 2 of D[13:0] and OVR relative to DRY give you the information you need to connect to flop flops on your FPGA.

    I hope this is what you're looking for.

    Thanks,

    Larry