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Synchronizing two AD9734s

I need to synchronize two AD9734s such that the two I and Q input words to the two DACs appear at the outputs of the two DACs with the same number of DACCLK cycle delays.  I'm assuming, since the DACCLKs are divided by two to produce the DATACLKs, that they will differ in phase by +/- 180 degrees.  First of all is the the right assumption?  Secondly will the internal LVDS receiver FIFOs in the two DACs have differing DACCLK delays?  I'm assuming so.  I have the ability to adjust the I and Q data inputs a number of DATACLK cycles relative to each other if need be.  However I would need to know the absolute relative delay of the DACs.  How can that be achieved?

Is there a preferred method for synchronizing the DATA delays of two AD9734 DACs?

Or is there a Dual DAC that can achieve 1200MSamples/S whereby both I and Q data inputs are operating at 1200MSamps/S?  ie no interpolation.

I haven't been able to find one though.

Any help would be much appreciated.

dmac

  • What kind of signal bandwidth do you need? You might look at the AD9142:

    http://www.analog.com/en/digital-to-analog-converters/high-speed-da-converters/ad9142/products/product.html

    The DACs are designed to be I/Q DACs and synchronized. There is an NCO and interpolators to enable lower data rates if you need a smaller bandwidth but want the RF output.

  • Thanks for the info Dan,

    I need 1100 Mbps input data rate and no interpolation.  So these parts won’t do that.  They only have 250Mbps input data rate.

    Signal bandwidth is 275 MHz in the baseband.  Symbol rate is 550MSymbols/S then I need 2X that for digital filtering.

    Don

  • Okay, I see. Then the AD9734 is the right part. Regarding synchronization of the two DACs, please refer to page 42 of the data sheet for a detailed description of how to sync two DACs. The FIFOs in the DACs will cause you to not know the relative position of your input data at power up, but the start-up routine to get the DACs sync'd is described. Once that is done and the DACs are put into Auto mode, they will be sync'd with each other. The DAC clock should be phase/delay matched from the source such that the DAC clock arrives at the two DACs at the same time.

  • The data sheet does not talk about synchronizing two DACs.  It does talk about centering the synch FIFO and how to tell how deep it is.  Also the FIFO can be bypassed.

    The data sheet discussion still leads me to think that there will be an ambiguity of +/- 180 degrees in the data clocks since they are derived by dividing the DACCLK by two.

    I suppose that I could measure the relative phase difference of the two DATACLKs and adjust the two I and Q data delays before they reach the DAC.  Then with the discussion on page 42 work to set the two I and Q DAC FIFOs to the same depth value or perhaps bypass them altogether.

     

    I’d be interested if there is any specific literature on a reliable method for synchronizing two AD9734 DACs.

    Thanks for your help

    dmac

  • Yes, sorry to not be clear, what you suggest is what I meant to suggest. There is no sync engine that will automatically sync the two DACs, but you can monitor the FIFO_STAT of the two DACs to determine their alignment relative to each other. You would want to run in Manual mode to ensure that one DAC's auto mode doesn't adjust itself without you knowing about it. When your FIFO_STAT monitor flags you that one or the other DAC is not centered, you can take action to adjust it as necesary.

    You would need to know the amount of delay from FPGA to each DAC and the DAC CLK delays. Ideally, the delays to each DAC are matched such that signals initiated at the same time on the FPGA will reach the DACs at the same time. Then, the FIFO depths need to be tracked and kept aligned.

    If you are trying to sync two DACs, you would only use one of the DATA CLOCK OUT signals, and only one DATA CLOCK IN signal, for both DACs, unless you think your bank-to-bank skew would dominate and you'd rather adjust two DATA CLOCK IN signals that are generated from one DATA CLOCK OUT. Using the one DCO would eliminate the 180 degree phase ambiguity you mention.

  • Much thanks Dan,

    I like the idea of using a data_out_clock from 1 dac to generate all I and Q Data and data_in_clks for both dacs.

    I wonder if bypassing the FIFO would work at 1.2Gsamps/Sec?

     

    All I and Q paths and Clocks will be matched in length and best efforts used to provide a clean minimal jitter 1.2GHz DACCLK.

    Don

  • This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

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