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AD9706 OTCM pin powered from ADP223 LDO

We have a development card using 2 x AD9706 DACs to drive a zero-IF IQ modulator that requires a DC bias of 1.15V. We have set the full scale current to 5mA (Radj = 6.45K). We have set the OTCM to 0.5V, derived from a ADP223 Dual LDO. We have a load resistance of 470 ohms. When the development card is powered up the OTCM pins on the 2 x DACs are both +0.5V. When the DACs are programmed and are being clocked the OTCM pins on both DACs increases to +2.2V for some reason. I have ADP223 powered on pin 6 from +3V3, the EN1 -  pin1 and EN2 - pin2 are connected to +3V3 for autostart, pin 3 is GND, pin 8 - ADJ1 is connected to pin 7 via a 0ohm resistor to provide +0.5V from VOUT1, and pin 4 - ADJ2 is connected to pin 5 via a 0ohm resistor to provide +0.5V from VOUT2. The GND paddle is connected to GND

If the +0.5V is derived from an external bench supply to both DACs the  OTCM pins remain at +0.5V even when the DAC clocks are running.

Can anyone offer any insight into why the OTCM pins are increasing in voltage to +2.2V when the DAC clocks are running, when derived from the ADP223 LDO?

**Update - We tried adding a potential divider to the ADP223 between the ADJ and VOUT pins, with values of 200k/200k. With no load we have +1V output from VOUT1 and VOUT2 as expected, but when we apply a load both outputs drop to +1.65V, which is around +0.5V less than where we were with 0R between the ADJ and VOUT pins, so there seems to be some kind of relationship between load/no load. Any ideas?

Darren

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  • Larry,

    We made some progress late yesterday with using the ADP223 with the DACs. In relation to the schematic I sent you yesterday, we fitted 49.9R to R100 and R102 so that we would have a least a 10mA load on each DAC on the OTCM pin. The voltage outputs from U15 - ADP223 (VOUT1 and VOUT2) are now stable at +0.5V with the DAC differential clocks running and the DAC outputs at the correct levels on both devices. Can you offer any explanation as to why the LDOs are now behaving themselves, is it simply that they require a minimum load on their outputs?

    I have attached a new schematic page showing the amendments that I have made. Can you confirm that the circuit looks correct?

    Regards,

    Darren

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  • Larry,

    We made some progress late yesterday with using the ADP223 with the DACs. In relation to the schematic I sent you yesterday, we fitted 49.9R to R100 and R102 so that we would have a least a 10mA load on each DAC on the OTCM pin. The voltage outputs from U15 - ADP223 (VOUT1 and VOUT2) are now stable at +0.5V with the DAC differential clocks running and the DAC outputs at the correct levels on both devices. Can you offer any explanation as to why the LDOs are now behaving themselves, is it simply that they require a minimum load on their outputs?

    I have attached a new schematic page showing the amendments that I have made. Can you confirm that the circuit looks correct?

    Regards,

    Darren

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