Sinc-Rolloff in AD9781

Hi,

We are currently using DAC in Normal Mode (Input BW = 50MHz and Sampling rate = 200MSPS). However we prefer not to have any attenuation over this band. However in the Transfer function figure shown in the datasheet, it seems the sinc roll-off will affect our signal. We would like to Pre-Equalise this Roll-off. Can you share us the sinc response of the DAC in tabular form so that it will be easier for us to implement pre-emphasis.

We are also interested in Return to Zero mode. It looks that in this mode, the roll-off will be minimum. Can you explain this mode? Will there be any effect on the DAC output while choosing this mode apart from output power reduction? Will there be any SNR degradation or any other issues to be considered in this mode?

  • 0
    •  Analog Employees 
    on Mar 12, 2013 7:14 PM

    We are currently using DAC in Normal Mode (Input BW = 50MHz and Sampling rate = 200MSPS). However we prefer not to have any attenuation over this band. However in the Transfer function figure shown in the datasheet, it seems the sinc roll-off will affect our signal. We would like to Pre-Equalise this Roll-off. Can you share us the sinc response of the DAC in tabular form so that it will be easier for us to implement pre-emphasis.

    This is stardard for all DACs

    Equation for SINC rolloff

    H(f) = SINC(PI*f/fs) = SIN(PI*f/fs)/ (PI*f/fs)

     

    are also interested in Return to Zero mode. It looks that in this mode, the roll-off will be minimum. Can you explain this mode? Will there be any effect on the DAC output while choosing this mode apart from output power reduction? Will there be any SNR degradation or any other issues to be considered in this mode?

    IWe clock data in on rising and falling edges of DAC clock (CLKP/N) on this DAC. In normal mode the same sample is clocked in twice. In Return to zero, sample is clocked on rising edge of DAC clock and a Zero value is clocked in on falling edges and in mixed mode the smaple is clocked in on rising edge an invereted sample is clocked in on the falling edge.

    the frequency response is shown below of all three modes is shown in Figure 65 of the data sheet.on page 29.

     

  • Hi,

    Since the RZ mode will sample only during Rising Edge, Can we use both the DACs (I&Q) for our application. Since both DAC inputs are sampled in DDR format, we cannot use RZ mode. Am I correct on this assumption?

    We are using both the DACs not as I & Q DAC but as two independent DACs (because IQ modulator is implemented on FPGA). Can these DACs be used independently?

  • 0
    •  Analog Employees 
    on Mar 13, 2013 6:39 PM

    Since the RZ mode will sample only during Rising Edge, Can we use both the DACs (I&Q) for our application. Since both DAC inputs are sampled in DDR format, we cannot use RZ mode. Am I correct on this assumption?

    no.

    You can use both DACs. Since the DCI and CLKP/N are the same frequency in your case 200MHz, the actual

    data rate coming in on the inputs is 400MSPS using DDR ( I  input on one edge Q sample on the other edge). The samples are clocked in on rising edge of CLK for both the I and Q DAC's and then midscleclocked to both to both on the falling edge for RZ mode.shown in figure 64.

    We are using both the DACs not as I & Q DAC but as two independent DACs (because IQ modulator is implemented on FPGA). Can these DACs be used independently?

    Yes they can be used as two real DACs or independent DACs. They have to use the same DAC sample rate defined by CLKP/N

  • Hi,

    As in Figure 64, both I and Q are sampled at Falling edge. Hence the clock input should be 400MHz, right? ie., the clock input should be twice that of what we give during Normal Mode.

  • 0
    •  Analog Employees 
    on Mar 13, 2013 11:07 PM

    As in Figure 64, both I and Q are sampled at Falling edge. Hence the clock input should be 400MHz, right? ie., the clock input should be twice that of what we give during Normal Mode.

    No, you are getting conused with DCI and DAT input with the CLK input that clocks the DACs.  The data input is clocked into the inputs on the rising and falling edge of DCI, I then Q. So for 200MSPS DAC rates the DCI frequency is 200MHz which provide data at 400MSPS using DDR (200MSPS to I and Q). If you used 400MHz DCI freq you wiould be loading in data at 800MSPS,400MSPS to each DAC.

    The part latches the input data then passes it to the DAC cores with a 7 CLK clock cylcle latency. The internal logic pairs the I and Q samples so the I and Q samples  get clock into the I and Q DACs on the same CLK edge. Depending on normal , RZ or Mixed mode changes what is clocked in every other CLK edge.