AD9705 with current mirror load

Within my current research project I'm using an AD9705 DAC loaded with a wilson current mirror. The output load of the current mirror is a 120 Ohm resistor. I've set the full scale current of the DAC to 2mA.

My problem is now, that at the moment when the current switches from 0 to 2mA the settling time is far too long (about 65ns) and I notice that the bits switch one after the other (MSB first, then second most significant bit, and so on). On each current level (for each bit) the output stays for about 10ns.

As I do not know anything about the internal circuitry of the DAC I cannot explain this behaviour.

As a further explanation I've attached a jpg showing the measured output (at the load of the current mirror = 120Ohm).

Please, can anyone help me to fix that problem?!

Thank you very much.

Robert

Parents
  • Hi Larry,

    if it is necessary, I can tell you more about my circuit. But I've already tried to drive a resistor instead of the current mirror (nothing else changed in my setup) and the result is as excepted: about 11ns settling time, no DAC samples noticeable.

    I'm driving the DAC with a single ended clock (CLK+, CLK- is left floating) which is generated within a FPGA. The frequency is 30MHz. For test purpose, the DAC data is the output of a 10bit-counter of the FPGA (as it is a 10bit DAC). CLK and DAC data waveform look as the have to, but I think this is not the problem, as it is obvious that the DAC gets it all well.

    Find attached the simplified (all relevant parts are included and not changed) schematic of my circuitry. The last page shows the DAC with the current mirror. The first two pages show the FPGA power supply and IO, the third page shows the board supply.

    Thank you!

    Robert

Reply
  • Hi Larry,

    if it is necessary, I can tell you more about my circuit. But I've already tried to drive a resistor instead of the current mirror (nothing else changed in my setup) and the result is as excepted: about 11ns settling time, no DAC samples noticeable.

    I'm driving the DAC with a single ended clock (CLK+, CLK- is left floating) which is generated within a FPGA. The frequency is 30MHz. For test purpose, the DAC data is the output of a 10bit-counter of the FPGA (as it is a 10bit DAC). CLK and DAC data waveform look as the have to, but I think this is not the problem, as it is obvious that the DAC gets it all well.

    Find attached the simplified (all relevant parts are included and not changed) schematic of my circuitry. The last page shows the DAC with the current mirror. The first two pages show the FPGA power supply and IO, the third page shows the board supply.

    Thank you!

    Robert

Children
No Data