AD9705 with current mirror load

Within my current research project I'm using an AD9705 DAC loaded with a wilson current mirror. The output load of the current mirror is a 120 Ohm resistor. I've set the full scale current of the DAC to 2mA.

My problem is now, that at the moment when the current switches from 0 to 2mA the settling time is far too long (about 65ns) and I notice that the bits switch one after the other (MSB first, then second most significant bit, and so on). On each current level (for each bit) the output stays for about 10ns.

As I do not know anything about the internal circuitry of the DAC I cannot explain this behaviour.

As a further explanation I've attached a jpg showing the measured output (at the load of the current mirror = 120Ohm).

Please, can anyone help me to fix that problem?!

Thank you very much.

Robert

  • 0
    •  Analog Employees 
    on Mar 25, 2013 5:29 PM

    Hi Robert -

    The attached scope capture shows normal behavior of the AD9705 driving a resistor.

    The rising edge of your pulse appears to be five 100ns samples. The settling time behavior looks good from my perspective. It's consistent with the 11ns settling time spec quoted in the data sheet. The AD9705 DAC core is a segmented current output DAC.

    Thanks,

    Larry

  • Hi Larry,

    thank you for your response. But unfortunately, I do not agree with you. The settling time, which is the time between starting the transition and reaching full scale current at the output, is in my measurement about 65ns, as I mentioned before. After this time, there is no longer a transition of any current switch noticeable, so I think the current has settled. If the DAC output drives a resistor, I would measure a similar output to that shown in your figure. There are no transitions of any single bit noticeable, the current increases from one state to the other continously. Unfortunately, within my measurement, it doesn't. But I don't know why.

    Regards,

    Robert

  • 0
    •  Analog Employees 
    on Mar 25, 2013 5:57 PM

    Hi Robert -

    From your waveform I would infer that you are running CLK+/CLK- at around 100Mhz. The rising edge of your waveform has six DAC samples, about 10ns each. Tha DAC cannot cause this on its own.

    If you'd like you can tell more about your circuit. (What does the clock look like?, What does the data look like?) This issue seem digital.

    - Larry

  • Hi Larry,

    if it is necessary, I can tell you more about my circuit. But I've already tried to drive a resistor instead of the current mirror (nothing else changed in my setup) and the result is as excepted: about 11ns settling time, no DAC samples noticeable.

    I'm driving the DAC with a single ended clock (CLK+, CLK- is left floating) which is generated within a FPGA. The frequency is 30MHz. For test purpose, the DAC data is the output of a 10bit-counter of the FPGA (as it is a 10bit DAC). CLK and DAC data waveform look as the have to, but I think this is not the problem, as it is obvious that the DAC gets it all well.

    Find attached the simplified (all relevant parts are included and not changed) schematic of my circuitry. The last page shows the DAC with the current mirror. The first two pages show the FPGA power supply and IO, the third page shows the board supply.

    Thank you!

    Robert

  • 0
    •  Analog Employees 
    on Mar 25, 2013 6:45 PM

    Hi -

    At 30Mhz the DAC will output a sample every 33.33ns. Your waveform has 3 output samples in 33.33ns. I suspect clock signal integrity here and suggest you look at that. There is no mechanism inside the DAC that can cause what you are seeing.

    - Larry