Help with AD5024

Hi Ivan,

I don't see anything wrong with your schematic. Can you post some plots of writing to the DAC? This sounds like an interface/software issue to me.

Hi Ivan,

Could you post a zoomed in plot of any of the "Write to and update DAC Channel n " writes. I'd like to see where the data edges with respect to the sclks.

It sounds like the data is shifted one bit to the right. If the Address bits were 0000 and this was the case D11 would be 0 so you would get 0 to 2.5V depending on what the rest of the bits were. When you write to DAC B A0 should be set to 1 but you could actually be setting D11 to 1 which would give you a voltage from 2.5V to 5V as you describe.

You can check this by multiplying whatever you write to the DAC by 2.

Regards,

KenK

Hi KenK,

Thank you very much for the quick response.

The test signal was maximum value (it must be 5V at the output).

0 - SCK, 1 - ~SYNC, 2 - DIN.

These are the plots:

In case of command "Write to Input Register n"

DAC A

DAC B

DAC C

DAC D

In case of command "Write to and update DAC Channel n "

DAC A

DAC B

DAC C

DAC D

If, for example, I send a sawtooth signal to DAC A in case of command "Write to Input Register n", I get it but within range of 0 - 2.5V.

If I do the same for DAC B. I get nothing on the Channel B, but I get sawtooth on the Channel A with 2.5V offset (2.5V - 5V).

For channels C and D exactly the same.

In case of command "Write to and update DAC Channel n" all the channels don't output at all.

Best regards,

Ivan

Hi KenK,

You can just click on the pictures and they'll be zoomed in. Or I misunderstood you?

Best regards,

Ivan

It's not quite clear from the pictures but it looks like you have data changing on the falling edge of the SCLK. It should change on the rising edge as shown in figure 4 of the data sheet.

Yes, you are right. It was my fault overlooked it in datasheet. I had to fasten the inverter to the SCK signal so everything works correctly.

Thank you very much for your help.

Best regards,

Ivan