AD9102 Output Signal

Hello Larry,

well that is a great shame. The utility of the chip has been severely compromised from my point of view - not wiring the Phase accumulator contents for triangle wave generation, and not allowing variable frequency AWG seems a huge loss of capability from what should have been simple given what is already in the chip.

I would not have used the chip if I had known these things. So as an AD insider, how does one go about improving the data sheet so that instead of saying

"The SRAM address counter can be programmed to be incremented by CLKP/CLKN (default) or by the rising edge of the DDS MSB" on page 23,

and again

"Selects the SRAM address counter clock as CLKP/CLKN when set to 0x0, DDS MSB when set to 0x1." in the Pattern Control 2 register description on page 34, both of which are WRONG, to say "but ONLY when the DDS Tuning word source is set to RAM data".

The designer needed his head read, I reckon.

So now I have two significant AD fails under my belt - the ADA4817 op-amp with a chip fault that drags the +IN pin to V- when powered down, and caused a great deal of angst on our part trying to re-design a 300 MHz capable work-around, and the AD9102, which we designed in on the strength of the data sheet, built a hundred boards, and find it can't do what the data sheet says. I am cross.

- Bart

Hello Larry,

well that is a great shame. The utility of the chip has been severely compromised from my point of view - not wiring the Phase accumulator contents for triangle wave generation, and not allowing variable frequency AWG seems a huge loss of capability from what should have been simple given what is already in the chip.

I would not have used the chip if I had known these things. So as an AD insider, how does one go about improving the data sheet so that instead of saying

"The SRAM address counter can be programmed to be incremented by CLKP/CLKN (default) or by the rising edge of the DDS MSB" on page 23,

and again

"Selects the SRAM address counter clock as CLKP/CLKN when set to 0x0, DDS MSB when set to 0x1." in the Pattern Control 2 register description on page 34, both of which are WRONG, to say "but ONLY when the DDS Tuning word source is set to RAM data".

The designer needed his head read, I reckon.

So now I have two significant AD fails under my belt - the ADA4817 op-amp with a chip fault that drags the +IN pin to V- when powered down, and caused a great deal of angst on our part trying to re-design a 300 MHz capable work-around, and the AD9102, which we designed in on the strength of the data sheet, built a hundred boards, and find it can't do what the data sheet says. I am cross.

- Bart