AD9102 Output Signal

Hello Larry,

sadly the link you included did not go anywhere. I did see your memory content. All I actually need is the very few register allocations to show how to make the RAM address use the DDS MSB as clock rather than the input clock.

Now I don't want to chirp the DDS, I want to output directly from the RAM, WITHOUT the DDS, but using the DDS_MSB as clock. (I do understand that this means I could get jitter of 1 CLK In period, but I can work around that).  I have this horrible feeling that the chip does not work this way. Yet another failing of the data sheet.

Currently this is my complete initialization (sig_gen_control_701 does the work of saving to the AD9102) to get going with:

Out_port(~ad9102_nTrigger, ad9102_nTrigger);          //Trigger is off

sig_gen_control_701(SPICONFIG, 0x0);    //use 4 wire mode

sig_gen_control_701(PAT_STATUS,0);      //stop patterns if they are on

sig_gen_control_701(POWERCONFIG,0);    //set the power config

sig_gen_control_701(CLOCKCONFIG,0);    //set the clock config

sig_gen_control_701(DDS_TW32, 0);         //initialize with 1000 Hz, in 10 Hz steps = 100. 0 in upper word

sig_gen_control_701(DDS_TW1, 100 <<8);   //1kHz, but in upper 8 bits of lower tuning word

//The important bit:

sig_gen_control_701(DDS_CONFIG, RAM_DDS_MSB_CLK); //the RAM sequence is output on the rising DDS MSB    <----- this is what I do, but it has no effect  (RAM_DDS_MSB_CLK = 0x04)

sig_gen_control_701(DAC_DGAIN, DAC_GAIN_x1 <<4);          //set the gain to 1

sig_gen_control_701(DACDOF, 0);                              //No offset

sig_gen_control_701(SAW_CONFIG, SAW_TRIANGLE);  //make the sawtooth a triangle, with 1 sample/step

sig_gen_control_701(WAV_CONFIG, 0);          //set the waveform to output from RAM from start to stop address

sig_gen_control_701(PAT_TYPE,0);        //repeat continuously

sig_gen_control_701(PAT_PERIOD,4000);   //the pattern is 4000 samples long - just to experiment with

sig_gen_control_701(START_ADDR,0<<4);      //set the start address to 0 - used for square wave output

sig_gen_control_701(STOP_ADDR,4000<<4);       //set end address inclusive

sig_gen_control_701(DAC_CST,0); //make sure constant value is 0   

sig_gen_control_701(PAT_STATUS,MEM_ACCESS); //access memory

for (n=0; n<2000; n++) sig_gen_control_701(SRAM_DATA+n,0x7fff);      //output minimum value for square wave

for (n=2000; n<4000; n++) sig_gen_control_701(SRAM_DATA+n,0x8000);      //output max value for square wave

sig_gen_control_701(SRAM_DATA+4000, 0); //output 0 value - just to check how start/stop address works

sig_gen_control_701(PAT_STATUS,1);      //start pattern

Out_port(~ad9102_nTrigger, 0);          //Trigger is on

My whole design was predicated on the chip working this way, and this is the way I read the data sheet. I am very sad that I cannot do a swept Triangle wave, and now it looks like I can't do a swept arbitrary wave either. I guess that means throwing away the board (made a 100 so far), and just using a DAC, and using the FPGA instead. I was trying to save time, but no. (As an aside this is the second AD disappointment this year. The first was major, and caused a complete extra design loop, with added component cost and loss of performance - I'm using the AD4817 op-amp, and discovered when you power it down that the +IN input gets dragged to -V, confirmed with the designer as a chip bug. Now I have to isolate the input with a relay. Blah).

regards

Bart

Hello Larry,

sadly the link you included did not go anywhere. I did see your memory content. All I actually need is the very few register allocations to show how to make the RAM address use the DDS MSB as clock rather than the input clock.

Now I don't want to chirp the DDS, I want to output directly from the RAM, WITHOUT the DDS, but using the DDS_MSB as clock. (I do understand that this means I could get jitter of 1 CLK In period, but I can work around that).  I have this horrible feeling that the chip does not work this way. Yet another failing of the data sheet.

Currently this is my complete initialization (sig_gen_control_701 does the work of saving to the AD9102) to get going with:

Out_port(~ad9102_nTrigger, ad9102_nTrigger);          //Trigger is off

sig_gen_control_701(SPICONFIG, 0x0);    //use 4 wire mode

sig_gen_control_701(PAT_STATUS,0);      //stop patterns if they are on

sig_gen_control_701(POWERCONFIG,0);    //set the power config

sig_gen_control_701(CLOCKCONFIG,0);    //set the clock config

sig_gen_control_701(DDS_TW32, 0);         //initialize with 1000 Hz, in 10 Hz steps = 100. 0 in upper word

sig_gen_control_701(DDS_TW1, 100 <<8);   //1kHz, but in upper 8 bits of lower tuning word

//The important bit:

sig_gen_control_701(DDS_CONFIG, RAM_DDS_MSB_CLK); //the RAM sequence is output on the rising DDS MSB    <----- this is what I do, but it has no effect  (RAM_DDS_MSB_CLK = 0x04)

sig_gen_control_701(DAC_DGAIN, DAC_GAIN_x1 <<4);          //set the gain to 1

sig_gen_control_701(DACDOF, 0);                              //No offset

sig_gen_control_701(SAW_CONFIG, SAW_TRIANGLE);  //make the sawtooth a triangle, with 1 sample/step

sig_gen_control_701(WAV_CONFIG, 0);          //set the waveform to output from RAM from start to stop address

sig_gen_control_701(PAT_TYPE,0);        //repeat continuously

sig_gen_control_701(PAT_PERIOD,4000);   //the pattern is 4000 samples long - just to experiment with

sig_gen_control_701(START_ADDR,0<<4);      //set the start address to 0 - used for square wave output

sig_gen_control_701(STOP_ADDR,4000<<4);       //set end address inclusive

sig_gen_control_701(DAC_CST,0); //make sure constant value is 0   

sig_gen_control_701(PAT_STATUS,MEM_ACCESS); //access memory

for (n=0; n<2000; n++) sig_gen_control_701(SRAM_DATA+n,0x7fff);      //output minimum value for square wave

for (n=2000; n<4000; n++) sig_gen_control_701(SRAM_DATA+n,0x8000);      //output max value for square wave

sig_gen_control_701(SRAM_DATA+4000, 0); //output 0 value - just to check how start/stop address works

sig_gen_control_701(PAT_STATUS,1);      //start pattern

Out_port(~ad9102_nTrigger, 0);          //Trigger is on

My whole design was predicated on the chip working this way, and this is the way I read the data sheet. I am very sad that I cannot do a swept Triangle wave, and now it looks like I can't do a swept arbitrary wave either. I guess that means throwing away the board (made a 100 so far), and just using a DAC, and using the FPGA instead. I was trying to save time, but no. (As an aside this is the second AD disappointment this year. The first was major, and caused a complete extra design loop, with added component cost and loss of performance - I'm using the AD4817 op-amp, and discovered when you power it down that the +IN input gets dragged to -V, confirmed with the designer as a chip bug. Now I have to isolate the input with a relay. Blah).

regards

Bart