AD9102 Output Signal

Hello Larry,

Yes it is true the paragraph discusses RAMUPDATE, but there is no example of a minimum control sequence in the data sheet, which I think many users would have found helpful (as evidenced by the number of people having problems with it!). My confusion initially was that I assumed (incorrectly) that the shadow registers were only used when running, and not all the time. In addition it appears that nTrigger is required to transition to start an output.

Other points that could be in the data sheet:

1. The time from reset to being able to program values, and the minimum duration of the reset pulse.

2. The format of the DAC_DGAIN value. The data sheet says -2 to +2. Is this two's compliment? I found 0x400 is x1.

3. Please be specific about the sample format saved to RAM. It appears that the sample is stored in [15:2], and not  [11:0] as Table 14 claims.

    A value of 0 is mid range, up to 0x1FFF <<2 denoting maximum +ve amplitude, and 0x2000 <<2 denoting maximum -ve amplitude, and

    0x3FFF <<2 being one count negative from the 0 point. 

4. Confirm what the Start Address means. I found that the address range programmed is 0 ..  0xFFF <<4.

5. Confirm that the output sequence goes from start address to stop address inclusive and not start address to stop address - 1.

6. Confirm that Ram Update is required both when the pattern is running, and also when it is not running.

7. Make clearer that you cannot change a pattern (eg DDS sine to RAM), unless the pattern is off first. 

8. I want to clock the RAM pattern at the rising edge of the DDS MSB rate. So I set DDS_CONFIG to 0x04 (bit 2 = 1), but this does not seem to work the way I expect.

9. The meaning of the DDS_PW (Phase Offset) is not defined. It is a 16 bit number. This suggests 0- 0xFFFF is 0 - 2pi radians. However, in my tests, I found the Phase register is not set absolutely (as in the AD9834), instead the DDS_PW represents an offset from the current phase value, which is random. It is not possible (please confirm) to reset the phase to a know angle (eg 0). This means we cannot start generating at a particular phase angle - most annoying. So what is the use of this register in a single channel application?

Anyway, the device is pretty good in some areas, so thanks - but I'm sad about the Triangle Wave generation, and Phase setting lackings.

Bart

Hello Larry,

Yes it is true the paragraph discusses RAMUPDATE, but there is no example of a minimum control sequence in the data sheet, which I think many users would have found helpful (as evidenced by the number of people having problems with it!). My confusion initially was that I assumed (incorrectly) that the shadow registers were only used when running, and not all the time. In addition it appears that nTrigger is required to transition to start an output.

Other points that could be in the data sheet:

1. The time from reset to being able to program values, and the minimum duration of the reset pulse.

2. The format of the DAC_DGAIN value. The data sheet says -2 to +2. Is this two's compliment? I found 0x400 is x1.

3. Please be specific about the sample format saved to RAM. It appears that the sample is stored in [15:2], and not  [11:0] as Table 14 claims.

    A value of 0 is mid range, up to 0x1FFF <<2 denoting maximum +ve amplitude, and 0x2000 <<2 denoting maximum -ve amplitude, and

    0x3FFF <<2 being one count negative from the 0 point. 

4. Confirm what the Start Address means. I found that the address range programmed is 0 ..  0xFFF <<4.

5. Confirm that the output sequence goes from start address to stop address inclusive and not start address to stop address - 1.

6. Confirm that Ram Update is required both when the pattern is running, and also when it is not running.

7. Make clearer that you cannot change a pattern (eg DDS sine to RAM), unless the pattern is off first. 

8. I want to clock the RAM pattern at the rising edge of the DDS MSB rate. So I set DDS_CONFIG to 0x04 (bit 2 = 1), but this does not seem to work the way I expect.

9. The meaning of the DDS_PW (Phase Offset) is not defined. It is a 16 bit number. This suggests 0- 0xFFFF is 0 - 2pi radians. However, in my tests, I found the Phase register is not set absolutely (as in the AD9834), instead the DDS_PW represents an offset from the current phase value, which is random. It is not possible (please confirm) to reset the phase to a know angle (eg 0). This means we cannot start generating at a particular phase angle - most annoying. So what is the use of this register in a single channel application?

Anyway, the device is pretty good in some areas, so thanks - but I'm sad about the Triangle Wave generation, and Phase setting lackings.

Bart