AD9102 Output Signal

Hi -

Yes the shadow register concept is expalined in the paragraph below from the data sheet. Teh idea is for the user to be able to update shadow registers while active registers are in use generating a signal. We're looking to continuosly improve our presentation of data sheet material. We will endeavor to get a better rating than appalling in the future.

Configuration Register Update Procedure

Most SPI accessible registers are double buffered. An active register set controls operation of the AD9102 during pattern generation. A set of shadow registers stores updated register values. Register updates can be written at any time. When configuration update is complete, the user writes a 1 to the UPDATE bit in the RAMUPDATE register. The UPDATE bit arms the register set for transfer from shadow registers to active registers. The AD9102

performs this transfer automatically the next time the pattern generator is off. This procedure does not apply to the 4k × 14 SRAM. For the SRAM update procedure, see the SRAM section.

Hi -

Yes the shadow register concept is expalined in the paragraph below from the data sheet. Teh idea is for the user to be able to update shadow registers while active registers are in use generating a signal. We're looking to continuosly improve our presentation of data sheet material. We will endeavor to get a better rating than appalling in the future.

Configuration Register Update Procedure

Most SPI accessible registers are double buffered. An active register set controls operation of the AD9102 during pattern generation. A set of shadow registers stores updated register values. Register updates can be written at any time. When configuration update is complete, the user writes a 1 to the UPDATE bit in the RAMUPDATE register. The UPDATE bit arms the register set for transfer from shadow registers to active registers. The AD9102

performs this transfer automatically the next time the pattern generator is off. This procedure does not apply to the 4k × 14 SRAM. For the SRAM update procedure, see the SRAM section.