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# AD9777 overall delay

Hi

I am using the AD9777 in an existing design of a digital feedback controller, so actual input-to-output time delay is critical.

What is this delay for the AD9777? (the datasheet only gives the settling time, measured from the start of the analog output).

Is the overall delay and "group delay" the same thing? The AD9777 datasheet lists "group delay" under terminology, but doesn't actually use the term anywhere else in the datasheet.

Kind regards

• In addition to the analog delay their is latency in the digital interface and interpolation.

The table shows latency in DAC clock periods. So it will depend on what intepolation and modulation is used.

The settling time is how long it takes the DAC core to settle when the digital code changes the full digital range.

it need to be added to the digital latency.

 AD977X Latency Table Interpolation Rate Modulation Rate Stage 1 Latency Stage 2 Latency Stage 3 Latency Modulator Latency Total Latency 2 1 56 0 0 0 56 2 2 56 0 0 20 76 2 4 56 0 0 22 78 2 8 56 0 0 21 77 4 1 112 34 0 0 146 4 2 112 34 0 20 166 4 4 112 34 0 22 168 4 8 112 34 0 21 167 8 1 224 68 24 0 316 8 2 224 68 24 20 336 8 4 224 68 24 22 338 8 8 224 68 24 21 337 Note: All latencies expressed in multiples of the DAC update rate, fDAC
• Thanks Tguy

This is very useful information. What is the digital delay with no (x1) interpolation and no (1x) modulation?

And as for the units, do I understand it correctly that ie. 2x interpolation 1x modulation would be 56 * 1/f_dac?

In this case, with an input data rate of 100msps, f_dac = 200msps => 5 ns period =>

Digital delay = 56 * 5ns = 250ns

Total delay = 250ns + settling time of ~11ns = =261ns.

• Unfortunately this is a very old part and the 1x delay information is not available. I estimate it would be about 10-15 DAC clock cycles. Is there any reason you are not using one of our newer products like the AD9125.

• I am using an existing controller I designed back in 2005. I am now trying to optimise the code to reduce latency (a critical parameter in closed-loop feedback).

Your estimates compared to my measured delays (1x interpol., 1x mod.):

Total delay 100ns @ 160 Msps less 11ns settling = 89ns =>  ~14 clock cycle delay (14.2)

Can recommend a lower latency DAC that

a) will be pin compatible with the AD9777, or

b) could be used in a future digital feedback controller design.

Optimising the delay is a big problem for me. The datasheets for high speed ADCs and DACs doesn't really specify the total delay. I need to close a high speed feedback loop with bandwidth DC to 10 MHz (or "few MHz"). I currently use the AD6640 with 2 cycle delay on the input and the AD9777 on the output.

• If you don't need interpolation the AD9747 Dual DAC offers the lowest latency, 7 clock cycles. It is not pin compatiable to the AD9777. We have not DACs pin compatiable to the AD9777 and we don't use that package type on new products.