I use a AD9117 with IQ modulator ADRF6755. I have used 50 Ohm 1% at the output of the DAC, balanced filter for limit bandwidth, 100 Ohm 1% to close filter at the input of ADRF6755. AD9117 generate 0.5V of pedestal and signal go from -0.45 to +0.45 V (0.90 Vpp). In this configuration, with my surprise, I have a "amplitude imbalance" of 2 % ... ... with change of Gain on "I path" I managed to get "amplitude imbalance" of 0.05 % ... ...
The DAC AD9117 have two pin for adjust current generator of DAC : FSADJI and FSADJQ with the respective resistance of 1.6K 1%.
For decrease the phenomenon I can connect FSADJI with FSADJQ together with a single resistor ?
What other measures can I use ?
Thanks very much.
In most of our DACs we don't specify the I to Q gain match. Most of the gain match error is due to the low pass filters which typically are made with 10% components. On most of our DACs you have to use the SPI registers to configure the part so the typical customer uses our offset, gain and phase adjust registers to cancel out the LO and Image. Only the AD9117 and AD9717 offer the pin mode options. You might consider adjusting full scale gain digitally from your FPGA or ASIC if you can't use the fine gain adjust SPI registers of the AD9117.
If I drive FSADJx with external buffered reference voltage ? I could improve the result ?
No that will improve the abopsute gain but does nothing for the I?Q gain match. The gain error match is from
the two I and Q control amp offset errors that set up full scale current.