AD9115 (AD9114 AD9116 AD9117) SPI Port Problems

We have built a prototype board using the AD9115 DAC and I’m trying to configure it using the SPI port and am having trouble.  Here’s what I’m doing and what I’m getting:

 

  • I power up the DAC and then toggle the RESET/PINMD pin from low to high to low to reset the spi port
  • I bring the CS pin low
  • I send 8 SLCK’s and transmit “0xE0” over the SDIO pin.  This should allow me to read 4 bytes from the DAC starting at address 0.
  • During the next 32 SCLK pulses I expect to read the default values from the first 4 registers, which are 0x00, 0x40, 0x34, 0x00.  But instead I’m reading 0xFF, 0x09, 0x00, 0x00.
  • I bring the CS pin back high

 

Writing to the chip and then trying to read what I just wrote gives similarly incorrect results.  Anyone have any experience writing and reading from the DAC that could help me figure out what's wrong?  Looking at the waveforms on the scope, everything seems to match the datasheet.  The CS pin goes low before the first SCLK edge, the data is changing state on the falling edge of SCLK so it's ready to be sampled on the rising edge.  The CS pin doesn't go high until after the very last SCLK edge of the 5th byte.  Sometimes the DAC will try to write to the SDIO pin while I'm trying to write the "0xE0" instruction, telling me that me and the DAC are obviously out of sync, but I have no idea how that could have happened when there's no stray SCLK edges or CS's.

 

Just for grins we put the part in pin mode and then we can at least get the DAC to output a waveform on the Iout and Qout pins, so it seems like the part is working OK otherwise.  We also tried replacing the DAC just in case the first one was damaged but have gotten similar (yet not identical) results out of the SPI port.

 

Any help will be appreciated.

Thanks

Brett

  • Bret,

      I have seen customers have issues when the pin reset was not done. You do need to pulse the reset pin to set the registers to default values, because there is no internal power on reset circuit.  Otherwise the default values are random from chip to chip prior to the pin reset.   A pulse reset pin 35 with 50ns pulse high is needed to ensure reset on this part. If you are using a shorter reset time maybe the default values are not getting reset.

                  

  • Thanks for the response.  I think the reset was part of the solution to my problem.  It looks like I had three things working against me.  The first was that I didn't realize that when the DAC is in MSB mode (the default) that not only means that the bits are transmitted MSB first, but it also means that multiple word transfers are transmitted in decrementing order.  So when I was asking for 4 bytes starting at address 0, I was receiving address 0, then address 1F, then 1E, then 1D... and I was expecting to get addr 0, 1, 2, 3.  My next problem was that I was not resetting the device.  And finally, I had forgotten that yesterday I changed the DATAIO pin type on my FPGA from a bidirectional to an output only.  Now that I have that fixed I am finally reading the correct default values from the DAC.  Thanks for your help.

    Brett

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