AD9119 clocking with ADF4350

Figure 148 in AD9119 datasheet shows a possible signal chain for the clock path base on ADF4350 PLL usage.

Figure 22 in ADF4350 datasheet shows the PLL output stage.

In my opinion, biasing is missing on the ADF4350 side since its output stage do not include any pullup resistors.  Unless Figure 22 is complete?  Or I misunderstand something?

AD9737A datasheet shows usage of ADF4350 as well in figure 174. Biasing is provided.  That looks good to me.

Comparing figure 173 and 174 brings me one question: is there any reason to have the 100 ohms resistor on one side or the other of the ac-coupling capacitors?

Thanks for your assistance,

Frédéric

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