AD9114/5/6/7 output stage voltage compliance

I have a question regarding the main DAC output of the AD9114 / AD9115 / AD9116 / AD9117.

Power is +3.3 V and for many reasons (cost, space, voltage supply and others) we need to get as much power as possible from the output stage to avoid an extra amplification stage. This means the FS current will be close to 20 mA and the impedance seen by the DAC output should be as high as the voltage compliance allows.

Differential to single-ended conversion is performed by a transformer as shown on Figure 102 of the Datasheet, which says the voltage compliance is 1 V at 20 mA FS current (page 44) and 0.8 V at 8 mA FS current (page 5).

I wonder what is the best center-tap voltage for optimum linearity. Is it 0 V ?Thus, one DAC outputs will be driven to negative potentials while the other is positive, reaching the threshold voltage of some intrisinc diode below -0.5 V.

Or should we introduce a parallel RC network between the center-tap and ground, so the center-tap would be at a slightly positive voltage ? This is what would happen if we used the internal resistors. But in transformer-coupled applications, the Datasheet does not recommend using the RLIN/RLIP/RLQN/RLQP pins.

Thanks for you opinion - we don't want  a poor design to compromize the AD9116's performance !

  • The optimum performance would be using 50 Ohm load resitors which yields a 0.5v common mode with outputs swinging 0 to 1v.

  • To make things clear :

    in this case, I will not use the RLIN, RLIP and CMLI pin at all, and leave them unconnected (same for the Q channel) ?

    I understand the IRCM and 62.5Ω resistors usage (or non-usage). But on figure 1 of the Datasheet, there is a small wire between the CMLI pin and the I DAC block. What does that wire symbolize ? Is it that the I DAC need to know the common-mode voltage, in this case CMLI would act as an input ?

    The functionning of the ouput stage is quite complex as it may adapt to various circumstances. I strongly encourage Datasheet writers to make their best efforts to clarify all this

  • The schematic is a very simplified  version of the of the actual schematic. the CML pins have to be tied to gnd(AVSS) directly or thru an external  common mode resistor to gnd when not using the internal CML resistors. We have made this very clear in the pin function descriptions Table 7.

     

    I DAC Output Common-Mode Level. When the internal on-chip (IR

    CML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IRCML) is disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor, s