AD9760 output constant

I am attempting to use the AD9760 DAC to prototype a design. It is connected to a Spartan-3E FPGA which is providing the data bits and clock at 3.3V to the DAC circuit. I also have the analog voltage at 3.3V provided by a separate power supply. I'm measuring the output on a Tektronix oscilloscope. I'm using a simple ramp signal as output to test the DAC circuit and range of the analog output. When the DAC is connected to the FPGA, the analog output observed on IOUTA is a constant 700mV (IOUTB = 40mV). The sample clock provided to the DAC is currently 1MHz. I have probed each of the data pins at the AD9760 pin to confirm the signal levels upon entry to the DAC and all measure 3.3V, as expected, and are toggling as expected. The clock signal was also confirmed to be clean and 3.3V. Since the data bits are supposed to be latched in parallel on the rising edge of the sample clock, I have tested the operation by shifting the data bits 90 and 180 degrees out of phase with the clock so the data is definitely stable when sampled by the DAC and confirmed the setup times are not being violated.

While debugging this circuit, I also detached the data lines from the FPGA and manually connected them to either power (3.3V) or ground. The FPGA is still providing the sampling clock at 1MHz. Here are a few of my observations:

Data_in: "1111111111" = 720mV on IOUTA

Data_in: "1100000000" = 480mV on IOUTA

Data_in: "1000000000" = 360mV on IOUTA

Data_in: "0000000000" = 40mV on IOUTA

Seeing a change in the analog output level when the data bits are manually configured (versus driven by FPGA logic) leads me to believe I have a problem with the data being latched from the FPGA? However, I've confirmed via the oscilloscope that the data bits are toggling and that the data is stable on the rising edge of the DAC sample clock.

I've attached a drawing of my circuit. Any help would be greatly appreciated.

  • It looks strange that the sum of both output voltages is not 0.96 V but rather close to 0.72 or 0.74 V.

    Have you checked voltage on all pins, including supply and ground ? Is pin 17 at 1.2 V ?

  • Hi -

    The REFIO voltage is also of interest.

    Thanks,

    Larry

  • Marc_2 wrote:

    It looks strange that the sum of both output voltages is not 0.96 V but rather close to 0.72 or 0.74 V.

    Have you checked voltage on all pins, including supply and ground ? Is pin 17 at 1.2 V ?

    I think I reported the wrong voltage on IOUTB when I have the DAC connected to the FPGA. When the FPGA is toggling the data pins (with a ramp signal) IOUTA = 700mV and IOUTB = 400mV (so roughly 1.1V).

    REFIO (pin 17) = 1.2V.

    Since I would like to use the internal reference voltage, REFLO is tied to ACOM.

    My ground pins are measuring approx 34mV when the circuit is active.

    I went back and re-measured all the pins when the data is tied all high and all low.

    "1111111111" : IOUTA = 860mV, IOUTB = 300mV, REFIO = 1.3V;

    "0000000000" : IOUTA = 140mV, IOUTB = 1.02V, REFIO = 1.3V;

    For both, DVDD and AVDD = 3.24V. DCOM and ACOM = 34mV. REFIO = 1.2V. COMP1 = 1.6V. COMP2 = 2V. FSADJ = 1.3V.

  • Hi -

    Please send me scope captures of your CLK signal and a data bit.

    Thanks,

    Larry

  • 0
    •  Analog Employees 
    on Aug 2, 2018 2:38 PM
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