High-speed DAC for 8-bits

I am interested in a DAC for 8-bts that can work at high speed with output of about 2 to 3 Volts. I am using a FPGA to generate 8 bits, which I need to convert into an analog voltage to drive an optical modulator, which requires a voltage in a range from 0 to up to about 2 to 3.5 volts to modulate the light. My application requires fast conversion: I would like to convert this 8-bit code into the analog voltage within 10 ns, so I would like to know which DAC chip I should use and if possible I would like to have an evaluation board for this chip.

Many thanks.

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  • Danf,

    We got the evaluation board for the chip AD9748, and I have a question about the input pins of the digital bits (DB0X-DB7X).

    In page 19 of the spec sheet of the AD9748 it indicates that the inputs in the "header" for DB0-7X are pins 27, 25, 23, 21, 19,17, 15 and 13, and DB0-7X are directed to the Digital bit inputs of the chip DB0-7. However, by looking at the evaluation board layout in page 21, these pins do not go to the right pin input of the chip, as described in page 7. Instead, it looks like to me that the "header" inputs corresponding to DB0-7X should be 15, 13, 11, 9, 7, 5, 3, 1, where the MSB (DB7) is pin 1.This would match the evaluation board layout and the in configuration of the chip in page 7.

    Could you please tell me if this is correct?

    Thank you

Reply
  • Danf,

    We got the evaluation board for the chip AD9748, and I have a question about the input pins of the digital bits (DB0X-DB7X).

    In page 19 of the spec sheet of the AD9748 it indicates that the inputs in the "header" for DB0-7X are pins 27, 25, 23, 21, 19,17, 15 and 13, and DB0-7X are directed to the Digital bit inputs of the chip DB0-7. However, by looking at the evaluation board layout in page 21, these pins do not go to the right pin input of the chip, as described in page 7. Instead, it looks like to me that the "header" inputs corresponding to DB0-7X should be 15, 13, 11, 9, 7, 5, 3, 1, where the MSB (DB7) is pin 1.This would match the evaluation board layout and the in configuration of the chip in page 7.

    Could you please tell me if this is correct?

    Thank you

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