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AD9106 Errata

Hello,

    According to the Rev. A datasheet for the AD9106, the DAC1 Digital Gain Register (DAC1_DGAIN) is defined as:

[15:4] -> DAC1_DIG_GAIN

[3:0]  -> Reserved

 

From empirical evidence, it looks like there is a silicon error which defines the bits as:

[15:12] -> DAC1_DIG_GAIN[11:8]

[11:8]  -> Reserved

[7:4] -> DAC1_DIG_GAIN[3:0]

[3:0] -> DAC1_DIG_GAIN[7:4]

 

Can anyone verify this behavior?

 

Thank you,

Aaron

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  • Hi Aaron -

    You've identified an error in the register map. I'll check it out in the lab and change the data sheet appropriatly.

    Thanks,

    Larry

  • I'm having difficulties with negative gain values (register value doesn't change) for the AD9106. Positive values work fine. What was the verdict on the register bits? At least in Rev B datasheet the register definition has not been changed.

    The datasheet describes the gain value as "12-bit gain factor that has a range of ±2.0."

    Based on this I would think that the DAC1_DIG_GAIN value is a signed 12-bit value where 0 sets 0 gain, -2048 sets -2.0 gain and 2047 sets almost +2.0 gain? Is this assumption correct?

    Best regards

    Pauli

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  • I'm having difficulties with negative gain values (register value doesn't change) for the AD9106. Positive values work fine. What was the verdict on the register bits? At least in Rev B datasheet the register definition has not been changed.

    The datasheet describes the gain value as "12-bit gain factor that has a range of ±2.0."

    Based on this I would think that the DAC1_DIG_GAIN value is a signed 12-bit value where 0 sets 0 gain, -2048 sets -2.0 gain and 2047 sets almost +2.0 gain? Is this assumption correct?

    Best regards

    Pauli

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