Hello,
According to the Rev. A datasheet for the AD9106, the DAC1 Digital Gain Register (DAC1_DGAIN) is defined as:
[15:4] -> DAC1_DIG_GAIN
[3:0] -> Reserved
From empirical evidence, it looks like there is a silicon error which defines the bits as:
[15:12] -> DAC1_DIG_GAIN[11:8]
[11:8] -> Reserved
[7:4] -> DAC1_DIG_GAIN[3:0]
[3:0] -> DAC1_DIG_GAIN[7:4]
Can anyone verify this behavior?
Thank you,
Aaron
