AD9106: a bunch of questions.

Thanks a lot for your reply, Larry!

There's still a few questions/uncertainties/remarks. I'm gonna revert the order again

1. In my revision (Rev. A, which I have from today's product page of the AD9106) of the datasheet, Fig.43 shows /TRIGGER low to PATTERN GENERATOR ON, which is what I referred to. However, your reply on my question 1 basically states what I expected. Namely that Pattern Delay + 1 CLKP/CLKN clock cycle after a TRIGGER falling edge, the pattern generator, and hence, the output is activated (if all necessary conditions, RUN bit, etc. are fulfilled of course). But what is then the 'Trigger to Output Delay' (96ns) on page 8? I really can't see where it appears in any of the figures on page 25. Can I ignore it then?

This information is really essential to me, because I'd like to synchronize a few of those AD9106. I have to know if they really behave like in figure 43. or if there suddenly appears a hidden uncertainty, jitter, delay or anything else.

2. + 3. If I get it right now, the pattern generator can only enter off state, when the current pattern period is over. In other words, I can't interrupt a pattern period. I can only make it stop by setting /TRIGGER high, clearing RUN, unset auto repeat or something like this, such that it ends when the current pattern period is over (and therefore also continuous mode doesn't ignore pattern periods). The output goes off when the current period is over iff I want it to, am I right? Or is there a way to interrupt the output in continuous wave mode during a pattern period without writing a zero in the amplitude register or similar? There is not any explicit figure or note about switching to off state during continuous mode in the datasheet, that's why I'm asking.

Edit: To make my point clear once more: If continuous waves are output during the duration of the pattern on state and the pattern on state ends only when a pattern period ends, then continuous waveform output can only end at the end of a pattern period and therewith doesn't completely ignore pattern period. This is what causes my confusion.

4. That completely answers question 4 to my entire satisfaction . Though, what I meant with the PHASE_MEM_EN bit was, that in "Table 63. Bit Descriptions for DDSx_CONFIG" in the description of PHASE_MEM_EN3 it says: "Since phase word is 8 bits and RAM data is 14 bit, only 8 MSB of RAM are taken into account.". Shouldn't it then rather read like "Since phase word is 16 bits..."?

5. Where can I find the information that I can only select this option if DDS tuning words are stored in the SRAM in the datasheet? This implies that I can do AM or PM not coherent to my output frequency, which is a quite relevant information!

If the SRAM address increments after one full cycle, then it doesn't increment with the "rising edge of the DDSx MSB" (I guess Most Significant Byte Edit: or Bit), but rather with the wrap of the DDSx.

Please enhance the quality of your datasheets! I'm not the only user, who catches some errors or lacks there (see e.g. the "Product reviews" of the AD9106). My intention is not to be unnecessarily fussy, but really to understand the theory of operation of your great products!

Thanks a lot for your reply, Larry!

There's still a few questions/uncertainties/remarks. I'm gonna revert the order again

1. In my revision (Rev. A, which I have from today's product page of the AD9106) of the datasheet, Fig.43 shows /TRIGGER low to PATTERN GENERATOR ON, which is what I referred to. However, your reply on my question 1 basically states what I expected. Namely that Pattern Delay + 1 CLKP/CLKN clock cycle after a TRIGGER falling edge, the pattern generator, and hence, the output is activated (if all necessary conditions, RUN bit, etc. are fulfilled of course). But what is then the 'Trigger to Output Delay' (96ns) on page 8? I really can't see where it appears in any of the figures on page 25. Can I ignore it then?

This information is really essential to me, because I'd like to synchronize a few of those AD9106. I have to know if they really behave like in figure 43. or if there suddenly appears a hidden uncertainty, jitter, delay or anything else.

2. + 3. If I get it right now, the pattern generator can only enter off state, when the current pattern period is over. In other words, I can't interrupt a pattern period. I can only make it stop by setting /TRIGGER high, clearing RUN, unset auto repeat or something like this, such that it ends when the current pattern period is over (and therefore also continuous mode doesn't ignore pattern periods). The output goes off when the current period is over iff I want it to, am I right? Or is there a way to interrupt the output in continuous wave mode during a pattern period without writing a zero in the amplitude register or similar? There is not any explicit figure or note about switching to off state during continuous mode in the datasheet, that's why I'm asking.

Edit: To make my point clear once more: If continuous waves are output during the duration of the pattern on state and the pattern on state ends only when a pattern period ends, then continuous waveform output can only end at the end of a pattern period and therewith doesn't completely ignore pattern period. This is what causes my confusion.

4. That completely answers question 4 to my entire satisfaction . Though, what I meant with the PHASE_MEM_EN bit was, that in "Table 63. Bit Descriptions for DDSx_CONFIG" in the description of PHASE_MEM_EN3 it says: "Since phase word is 8 bits and RAM data is 14 bit, only 8 MSB of RAM are taken into account.". Shouldn't it then rather read like "Since phase word is 16 bits..."?

5. Where can I find the information that I can only select this option if DDS tuning words are stored in the SRAM in the datasheet? This implies that I can do AM or PM not coherent to my output frequency, which is a quite relevant information!

If the SRAM address increments after one full cycle, then it doesn't increment with the "rising edge of the DDSx MSB" (I guess Most Significant Byte Edit: or Bit), but rather with the wrap of the DDSx.

Please enhance the quality of your datasheets! I'm not the only user, who catches some errors or lacks there (see e.g. the "Product reviews" of the AD9106). My intention is not to be unnecessarily fussy, but really to understand the theory of operation of your great products!