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The AD9106 TxDAC® and waveform generator is a high performance, quad digital-to-analog converter (DAC) integrating on-chip pattern memory for complex waveform...
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AD9106 on Analog.com

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AD9106: a bunch of questions.



		

			

									
					    herrkami
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Nov 28, 2014 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    Hi, 
    
 
    I have already studied the datasheet (Rev. A) quite a time, but I can't solve a few questions by myself: 
    
 
    1. What is the 'Trigger to Output Delay' (p.8)? Especially when considering Fig. 43? 
    
 
    2. What does 'Continuous waveforms ignore pattern periods.' (p.25) exactly mean? Focus lies on 'period'. This also leads me to my third question: 
    
 
    3. WAVE_SELx offers two unmodulated prestored waveform modes, with and without 'START_DELAYx and PATTERN_PERIOD'. The difference is clear to me, but I couldn't find out when the waveforms stop in those two cases. Probably at the end of the pattern period ? 
    
 
    4. How long is the phase offset word? The descriptions for DDSx_PHASE don't mention a restriction, although 16 bit long, but in a sidenote in the description of the PHASE_MEM_EN3 bit, it says 8 bit. Is this right, (and if yes, why not more????)? If so, please make this more visible in future revisions of the datasheet. 
    
 
    5. On p.27 it says 'Each of the SRAM address counters can be programmed to be incremented by CLKP/CLKN (default) or by the rising edge of the DDSx MSB.'. The rising edge of a byte? Could you please explain this to me? 
    
 
    Sorry for all those questions, but they are quite relevant to my design considerations. Thanks in advance, 
    
 
    Kami 
    
								
    

				
				
		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    


	
    
		
	
    















    
	
    
	
    
					



			








	
	
	
	



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      •  Analog Employees  
      
            
			                            
                        
                on Dec 3, 2014 1:43 AM
            
            
					
      
	
      

		
		
      
					
      Hi -
      
 
      on #5, The SRAM address increment clock is always CLKP/CLKN except if the SRAM contains DDS tuning words. In this case the user may elect to use CLKP/CLKN or the MSB of the DDS output. Using the MSB of the DDS output causes the DDS to dwell on each frequency setting for one full cycle.
      
 
      on #4, The DDS phase adjust words are called DDSx_PW and are 16 bits wide. The range of phase offset is 0 to 360 degrees. The resolution is .055 degree. PHASE_MEM_EN is just bit 1 of the DDS_CONFIG register.
      
 
      on #3, The PATTERN_RPT bit in the PAT_TYPE register (Register 0x1F[0]) controls whether the pattern output auto repeats (periodic pulse train repeats indefinitely) or repeats a number of consecutive times defined by the DAC_REPEAT_CYCLE bits in Register 0x2B. The latter are periodic pulse trains that repeat a finite number of times. 
      
 
      0n #2, Continuous waveforms are output by the DAC for the duration of the pattern on state of the pattern generator. They are not generated on a pattern period by pattern period basis.
      
 
      On #1, Pattern Delay + 1 CLKP/CLKN clock cycle to enter the "pattern generator on" state following a TRIGGER falling edge with RUN bit set high. Figure 42 shows trigger high to output off. If TRIGGER is set high while a pattern is running, the output shut off is at the end of the current pattern period. Figure 43 shows RUN bit low to output off. RUN is set low while a pattern is running,  the output shut off is at the end of the current pattern period.
      
 
      Thanks,
      
 
      Larry
      
 

       
      
			
      

		
		
		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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													0
							
			
				
									
							        
			
			
			
      •  Analog Employees  
      
            
			                            
                        
                on Dec 3, 2014 1:43 AM
            
            
					
      
	
      

		
		
      
					
      Hi -
      
 
      on #5, The SRAM address increment clock is always CLKP/CLKN except if the SRAM contains DDS tuning words. In this case the user may elect to use CLKP/CLKN or the MSB of the DDS output. Using the MSB of the DDS output causes the DDS to dwell on each frequency setting for one full cycle.
      
 
      on #4, The DDS phase adjust words are called DDSx_PW and are 16 bits wide. The range of phase offset is 0 to 360 degrees. The resolution is .055 degree. PHASE_MEM_EN is just bit 1 of the DDS_CONFIG register.
      
 
      on #3, The PATTERN_RPT bit in the PAT_TYPE register (Register 0x1F[0]) controls whether the pattern output auto repeats (periodic pulse train repeats indefinitely) or repeats a number of consecutive times defined by the DAC_REPEAT_CYCLE bits in Register 0x2B. The latter are periodic pulse trains that repeat a finite number of times. 
      
 
      0n #2, Continuous waveforms are output by the DAC for the duration of the pattern on state of the pattern generator. They are not generated on a pattern period by pattern period basis.
      
 
      On #1, Pattern Delay + 1 CLKP/CLKN clock cycle to enter the "pattern generator on" state following a TRIGGER falling edge with RUN bit set high. Figure 42 shows trigger high to output off. If TRIGGER is set high while a pattern is running, the output shut off is at the end of the current pattern period. Figure 43 shows RUN bit low to output off. RUN is set low while a pattern is running,  the output shut off is at the end of the current pattern period.
      
 
      Thanks,
      
 
      Larry
      
 

       
      
			
      

		
		
		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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