AD9106: a bunch of questions.

Question

Hi, 
 I have already studied the datasheet (Rev. A) quite a time, but I can't solve a few questions by myself: 
 1. What is the 'Trigger to Output Delay' (p.8)? Especially when considering Fig. 43? 
 2. What does 'Continuous waveforms ignore pattern periods.' (p.25) exactly mean? Focus lies on 'period'. This also leads me to my third question: 
 3. WAVE_SELx offers two unmodulated prestored waveform modes, with and without 'START_DELAYx and PATTERN_PERIOD'. The difference is clear to me, but I couldn't find out when the waveforms stop in those two cases. Probably at the end of the pattern period ? 
 4. How long is the phase offset word? The descriptions for DDSx_PHASE don't mention a restriction, although 16 bit long, but in a sidenote in the description of the PHASE_MEM_EN3 bit, it says 8 bit. Is this right, (and if yes, why not more????)? If so, please make this more visible in future revisions of the datasheet. 
 5. On p.27 it says 'Each of the SRAM address counters can be programmed to be incremented by CLKP/CLKN (default) or by the rising edge of the DDSx MSB.'. The rising edge of a byte? Could you please explain this to me? 
 Sorry for all those questions, but they are quite relevant to my design considerations. Thanks in advance, 
 Kami

ADIApproved · Accepted Answer

Hi - 
 on #5, The SRAM address increment clock is always CLKP/CLKN except if the SRAM contains DDS tuning words. In this case the user may elect to use CLKP/CLKN or the MSB of the DDS output. Using the MSB of the DDS output causes the DDS to dwell on each frequency setting for one full cycle. 
 on #4, The DDS phase adjust words are called DDSx_PW and are 16 bits wide. The range of phase offset is 0 to 360 degrees. The resolution is .055 degree. PHASE_MEM_EN is just bit 1 of the DDS_CONFIG register. 
 on #3, The PATTERN_RPT bit in the PAT_TYPE register (Register 0x1F[0]) controls whether the pattern output auto repeats (periodic pulse train repeats indefinitely) or repeats a number of consecutive times defined by the DAC_REPEAT_CYCLE bits in Register 0x2B. The latter are periodic pulse trains that repeat a finite number of times. 
 0n #2, Continuous waveforms are output by the DAC for the duration of the pattern on state of the pattern generator. They are not generated on a pattern period by pattern period basis. 
 On #1, Pattern Delay + 1 CLKP/CLKN clock cycle to enter the "pattern generator on" state following a TRIGGER falling edge with RUN bit set high. Figure 42 shows trigger high to output off. If TRIGGER is set high while a pattern is running, the output shut off is at the end of the current pattern period. Figure 43 shows RUN bit low to output off. RUN is set low while a pattern is running, the output shut off is at the end of the current pattern period. 
 Thanks, 
 Larry)

ADIApproved · Answer

1. 96ns is 17.5 180Mhz CLKP/CLKN clock cycles. So my answer to 1 from yesterday should have been Pattren Delay + 17.5 CLKP/CLKN clock cycles to enter the pattern generator on state. 
 2 + 3. Everything you've stated is correct. 
 5. A new revision of the AD9106 data sheet is being worked on that includes this.

Electronic Design Services - PartnerZone

Products Mentioned

AD9106: a bunch of questions.