AD9106: a bunch of questions.

Hi,

I have moved this question to the high-speed DACs. Someone should be able to assist you here.

-Sittie

Hi -

on #5, The SRAM address increment clock is always CLKP/CLKN except if the SRAM contains DDS tuning words. In this case the user may elect to use CLKP/CLKN or the MSB of the DDS output. Using the MSB of the DDS output causes the DDS to dwell on each frequency setting for one full cycle.

on #4, The DDS phase adjust words are called DDSx_PW and are 16 bits wide. The range of phase offset is 0 to 360 degrees. The resolution is .055 degree. PHASE_MEM_EN is just bit 1 of the DDS_CONFIG register.

on #3, The PATTERN_RPT bit in the PAT_TYPE register (Register 0x1F[0]) controls whether the pattern output auto repeats (periodic pulse train repeats indefinitely) or repeats a number of consecutive times defined by the DAC_REPEAT_CYCLE bits in Register 0x2B. The latter are periodic pulse trains that repeat a finite number of times.

0n #2, Continuous waveforms are output by the DAC for the duration of the pattern on state of the pattern generator. They are not generated on a pattern period by pattern period basis.

On #1, Pattern Delay + 1 CLKP/CLKN clock cycle to enter the "pattern generator on" state following a TRIGGER falling edge with RUN bit set high. Figure 42 shows trigger high to output off. If TRIGGER is set high while a pattern is running, the output shut off is at the end of the current pattern period. Figure 43 shows RUN bit low to output off. RUN is set low while a pattern is running,  the output shut off is at the end of the current pattern period.

Thanks,

Larry

Thanks a lot for your reply, Larry!

There's still a few questions/uncertainties/remarks. I'm gonna revert the order again

1. In my revision (Rev. A, which I have from today's product page of the AD9106) of the datasheet, Fig.43 shows /TRIGGER low to PATTERN GENERATOR ON, which is what I referred to. However, your reply on my question 1 basically states what I expected. Namely that Pattern Delay + 1 CLKP/CLKN clock cycle after a TRIGGER falling edge, the pattern generator, and hence, the output is activated (if all necessary conditions, RUN bit, etc. are fulfilled of course). But what is then the 'Trigger to Output Delay' (96ns) on page 8? I really can't see where it appears in any of the figures on page 25. Can I ignore it then?

This information is really essential to me, because I'd like to synchronize a few of those AD9106. I have to know if they really behave like in figure 43. or if there suddenly appears a hidden uncertainty, jitter, delay or anything else.

2. + 3. If I get it right now, the pattern generator can only enter off state, when the current pattern period is over. In other words, I can't interrupt a pattern period. I can only make it stop by setting /TRIGGER high, clearing RUN, unset auto repeat or something like this, such that it ends when the current pattern period is over (and therefore also continuous mode doesn't ignore pattern periods). The output goes off when the current period is over iff I want it to, am I right? Or is there a way to interrupt the output in continuous wave mode during a pattern period without writing a zero in the amplitude register or similar? There is not any explicit figure or note about switching to off state during continuous mode in the datasheet, that's why I'm asking.

Edit: To make my point clear once more: If continuous waves are output during the duration of the pattern on state and the pattern on state ends only when a pattern period ends, then continuous waveform output can only end at the end of a pattern period and therewith doesn't completely ignore pattern period. This is what causes my confusion.

4. That completely answers question 4 to my entire satisfaction . Though, what I meant with the PHASE_MEM_EN bit was, that in "Table 63. Bit Descriptions for DDSx_CONFIG" in the description of PHASE_MEM_EN3 it says: "Since phase word is 8 bits and RAM data is 14 bit, only 8 MSB of RAM are taken into account.". Shouldn't it then rather read like "Since phase word is 16 bits..."?

5. Where can I find the information that I can only select this option if DDS tuning words are stored in the SRAM in the datasheet? This implies that I can do AM or PM not coherent to my output frequency, which is a quite relevant information!

If the SRAM address increments after one full cycle, then it doesn't increment with the "rising edge of the DDSx MSB" (I guess Most Significant Byte Edit: or Bit), but rather with the wrap of the DDSx.

Please enhance the quality of your datasheets! I'm not the only user, who catches some errors or lacks there (see e.g. the "Product reviews" of the AD9106). My intention is not to be unnecessarily fussy, but really to understand the theory of operation of your great products!

1. 96ns is 17.5 180Mhz CLKP/CLKN clock cycles. So my answer to 1 from yesterday should have been Pattren Delay + 17.5 CLKP/CLKN clock cycles to enter the pattern generator on state.

2 + 3. Everything you've stated is correct.

5. A new revision of the AD9106 data sheet is being worked on that includes this.

Thank you again!

Hm, 17.5 CLKP/CLKN clock cycles sounds like sometimes 17 and sometimes 18 and less for lower sample clocks. I probably have to add variable delay lines in front of each AD9106, since this is not reliable.

Hi Korbinian -

Is this answered as far as you're concerned? Is there anything else you require?

Thanks,

Larry

Hello Larry,

I am interested in using the evaluation board for an application which requires good phase resolution.  If the phase word is 16 bits, will the resolution be (360-0)/(2^16) = 0.0055 degrees?  You're reply to (4) says that the resolution is 0.055 degrees.  Is that a misprint?  Sorry if this is an uninformed question.  I am just learning about DDS and this is my first post to the engineer zone.

Thank you,

Tal