AD9106 SRAM read/write

Hi Thomas -

The shadow register concept does not apply to SRAM. There is no set of shadow registers. You are reading and writing SRAM directly in locations 0x6000 through 0x6FFF using the procedure on page 27. I hope this helps.

Thanks,

Larry

I believe so.  This is the flow that I'm currently doing.

Write 0x0004 to 0x001E, CS toggle, write 0x0001 to 0x001D, CS toggle, write data to 0x6000 - 0x6FFF, CS toggle, write 0x000C to 0x001E, CS toggle, write 0x0001 to 0x001D, CS toggle, read data from 0x6000 - 0x6FFF.

So, apparently the reserved bits in SRAM are actually [3:0] not [15:12].  That's a pretty big mistake in the datasheet.  I'm getting values written to and read from the SRAM now but only if I address each data value first.  It doesn't work if I just try and write/read sequentially with one command and holding the CS line low for the sequential data.

Please call me directly at 781 937 1143

Thanks,

Larry

I would prefer this forum as phone service in the lab here is none existent at best and I have to step out to call.

Is the Sclk supposed to be high or low while idle?

Are the values for the SRAM left or right justified?

Are the values for the SRAM 2's compliment?

Does holding the CS line low increment, decrement or not increment the address pointer?

Hi -

This inquiry is being handled through direct email.

Thanks,

Larry

I've attached the email trail that answers this item

Assumed answered offline.