Questions about AD9146 frequence

Hi Sir:

 

 

We are surveying dual channel 1GSPS DAC for my project of network analyzer.

But I have some questions on AD9146.

 

We plan to generate DC~250MHz I/Q signal randomly.

In AD9146 datasheet page7, I do not understand.

 

If we bypass HB1 and HB2, using interpolation 1X, the data interface can be 1200MSPS. Why f_DAC=300MSPS?

 

With 2X and 4X interpolation, these number does not make sense to me either.

 

Could you help me clarify how these number come from and the suggested mode for our application?

 

Thanks and B.R.

Wen

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  • 0
    •  Analog Employees 
    on Mar 20, 2015 7:19 PM

    Hi Wen,

    The table you are referring to shows the different maximum speeds for each of the parts of the DAC.  The interface has a maximum rate of 1200MSPS with nominal supply (1.8V +/-5%).  Since this part is byte-wide, it requires one full DCI cycle (rising and falling edge) to clock in a full 16 bit word sample for one of the DACs.  Therefore if you're running the DAC at 300MHz in 1x interpolation, your DCI rate needs to be 600MHz (double data rate so effectively sending twice the amount of data, hence 1200MSPS).  Similarly for 2x interpolation if the DAC is running at 600MHz the DCI rate must be 600MHz also to transfer one full 16 bit word to both DACs on chip (two full DCI cycles) to line up with the sampling of the DAC.  The table shows the breakdown of how the maximum interface speed corresponds to the maximum DAC rate for a given interpolation.

    Therefore if you're looking to send a signal with 250MHz of bandwidth this won't be achievable with this part as the maximum instantaneous bandwidth is 150MHz.  If you don't need that wide of an instantaneous bandwidth you may be able to use the coarse modulation feature implemented in the code when you need to modulate a signal above 150MHz up to 250MHz.

    Thanks,

    Michele

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  • 0
    •  Analog Employees 
    on Mar 20, 2015 7:19 PM

    Hi Wen,

    The table you are referring to shows the different maximum speeds for each of the parts of the DAC.  The interface has a maximum rate of 1200MSPS with nominal supply (1.8V +/-5%).  Since this part is byte-wide, it requires one full DCI cycle (rising and falling edge) to clock in a full 16 bit word sample for one of the DACs.  Therefore if you're running the DAC at 300MHz in 1x interpolation, your DCI rate needs to be 600MHz (double data rate so effectively sending twice the amount of data, hence 1200MSPS).  Similarly for 2x interpolation if the DAC is running at 600MHz the DCI rate must be 600MHz also to transfer one full 16 bit word to both DACs on chip (two full DCI cycles) to line up with the sampling of the DAC.  The table shows the breakdown of how the maximum interface speed corresponds to the maximum DAC rate for a given interpolation.

    Therefore if you're looking to send a signal with 250MHz of bandwidth this won't be achievable with this part as the maximum instantaneous bandwidth is 150MHz.  If you don't need that wide of an instantaneous bandwidth you may be able to use the coarse modulation feature implemented in the code when you need to modulate a signal above 150MHz up to 250MHz.

    Thanks,

    Michele

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