AD9707 Serial Timing Specifications?

Hi,Larry-san

Thank you for reply.

But I can't understand about SPI Register Read Timming.

The tSU, setup time, following the falling edge of SCLK is the 2ns max.?

The tHLD, hold time, following the falling edge of SCLK is the 0ns max.?

How to consider the relation between the falling edge of SCLK and tSU,tHLD?

Best Regards,

sss

Hi -

The timing specs in table 6 apply to the SPI signals as well as data inputs. The maximum SCLK frequency is 20Mhz (in text on page 31).

tSCLK = 50ns  minimum

tDS = tS from table 6

tDH = tHLD = tH from table 6

tPWL = 25ns minimum

tPWH = 25ns minimum

SPI read data is driven out of the AD9707 2ns max following the falling edge of SCLK. Please disregard figure 77. It needs to be replaced.

Thanks,

Larry

From Figure 77, tSU and tHLD refer to the rising edge of SCLK.

From Table 6, 2ns and 0ns is the minimum requirement.