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AD9707 Production
The AD9704/AD9705/AD9706/AD9707 are the fourth-generation family in the TxDAC series of high performance, CMOS digital-to-analog converters (DACs). This...
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AD9707 on Analog.com

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AD9707 SPI read operation

		
	
				

			

									
					    sss
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Apr 13, 2015 
				
			
			
		
    
		
		                     
				
        		
    
		    
		    		    
		    			
    
			    
    Hi,all.
    
 
    In the datasheet @ AD9707,
    
 
    how long time is the setup and hold time specification, on the falling edge of SCLK, at SPI read operation ?
    
 
    Best Regards,
    
 
    sss
    
			
    
			
									
		                             
                        

    
    
                                            
                 Standard High Speed D/A Converters
                
                                                    
                 spi
                
                                                    
                 High Speed D/A Converters =30MSPS
                
                                                    
                 high speed dac
                
                                                    
                 ad9707
                
                                
            
    
    
    
		
    

				
				        
        		
    
			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		
    

        
        
        
    
					
    
			
    


    
















    
	
    
	
    
					



			








	
	
	
	



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                on Apr 14, 2015 8:43 PM
            
            
						
			            		
        
		
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        Hi,Larry-san
        
 
         
        
 
        Thank you for the reply.
        
 
        Please let me know if my understanding is correct.
        
 
        The tSU, setup time, following the falling edge of SCLK is the 2ns min.
        
 
        The tHLD, hold time, following the falling edge of SCLK is the 0ns min.? and max.?
        
 
        The hold time equals to the SCLK to SDIO Data Valid Time ?
        
 
        Best Regards,
        
 
        sss
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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                on Apr 14, 2015 8:43 PM
            
            
						
			            		
          
		
										0
					
	
          

		
		
          
		
          
                                
                                                            
          
					
          Hi,Larry-san
          
 
           
          
 
          Thank you for the reply.
          
 
          Please let me know if my understanding is correct.
          
 
          The tSU, setup time, following the falling edge of SCLK is the 2ns min.
          
 
          The tHLD, hold time, following the falling edge of SCLK is the 0ns min.? and max.?
          
 
          The hold time equals to the SCLK to SDIO Data Valid Time ?
          
 
          Best Regards,
          
 
          sss
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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