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The AD9102 TxDAC and waveform generator is a high performance digital-to-analog converter (DAC) integrating on-chip pattern memory for complex waveform...
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AD9102 on Analog.com

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AD9102 - Trouble with DDS mode and reading from SRAM??



		

			

									
					    daniel1.hong@intel.com
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Jul 22, 2015 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    I have the AD9102 EVboard and I can get all modes to work: constant value, Sawtooth, DDS, and reading from SRAM.  However, on my proto-layout board, I program the Ad9102 SPI directly and I can only get the constant value and Sawtooth mode to work.  The DDS and read from SRAM do not give any output.  I am taking the regval and default sequence from the EVboard software and and programming into AD9102 SPI directly.  So inputting example4 settings gives me the pulsed triangle wave for the sawtooth mode which is working, but the sine wave of example6 is not working.  The registers and SRAM are able to read and write properly. Is this a common problem or am I missing something obvious?  Any help would be appreciated, thanks.
    
									
			        
		
    

				
						
        

    
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                 ad9102
                
                                                    
                 clock and timing
                
                                                    
                 Direct Digital Synthesis (DDS)
                
                                
            
    
    
    

		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    
















    
	
    
	
    
					



			








	
	
	
	



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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Aug 7, 2015 2:07 AM
            
            
					
      
	
      

		
		
      
					
      Hi Dan,
      
 
           AD9120 power operation range can be from 1.8V to 3.3V. that's much more flexible, but you still may need to check if there has the big voltage drop or ripple/spur on each power rail. If you can send me the schematic, that will be helpful for understanding the issue deeply. You are using LDO or DC-DC regulator?
      
 
          Also the RESET pin connection needs to be looked into carefully. making sure it's clean.
      
 
          Example 1 or 2 configuration sequence is correct. RAMUPDATE can't reset all the registers to default values.
      
 
          Read or write SRAM shall follow the configuration mentioned in datasheet. Also Start_ADDR/STOP_ADDR should be configured correctly.
      
 
           To write to any SRAM address, set up the PAT_STATUS register (Register 0x1E) as follows:
      
 
       BUF_READ = 0 
      
 
           MEM_ACCESS = 1 
      
 
           RUN = 0
      
 
       To read data from any SRAM address, set up the PAT_STATUS as follows: 
      
 
           BUF_READ = 1 
      
 
           MEM_ACCESS = 1 
      
 
           RUN = 0 
      
 
      please make sure all the registers and SRAM can be written or read correctly.
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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													0
							
			
				
									
							        
			
			
			
      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Aug 7, 2015 2:07 AM
            
            
					
      
	
      

		
		
      
					
      Hi Dan,
      
 
           AD9120 power operation range can be from 1.8V to 3.3V. that's much more flexible, but you still may need to check if there has the big voltage drop or ripple/spur on each power rail. If you can send me the schematic, that will be helpful for understanding the issue deeply. You are using LDO or DC-DC regulator?
      
 
          Also the RESET pin connection needs to be looked into carefully. making sure it's clean.
      
 
          Example 1 or 2 configuration sequence is correct. RAMUPDATE can't reset all the registers to default values.
      
 
          Read or write SRAM shall follow the configuration mentioned in datasheet. Also Start_ADDR/STOP_ADDR should be configured correctly.
      
 
           To write to any SRAM address, set up the PAT_STATUS register (Register 0x1E) as follows:
      
 
       BUF_READ = 0 
      
 
           MEM_ACCESS = 1 
      
 
           RUN = 0
      
 
       To read data from any SRAM address, set up the PAT_STATUS as follows: 
      
 
           BUF_READ = 1 
      
 
           MEM_ACCESS = 1 
      
 
           RUN = 0 
      
 
      please make sure all the registers and SRAM can be written or read correctly.
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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