AD9125 internal NCO

Hello I have a development running inside a design house and I have been asked for this support:

They are trying to use the internal NCO from the DAC to shift the frequency of the input sine wave.

With that  it would be possible inject a sine to 7.8125Mhz in DAC(32 samples with the interface / NCO of the FPGA to 250Mhz), to have more samples per full wave, and increase its output frequency with the internal DAC NCO.

However, they can only configure the internal NCO with the same frequency of the input coming from the FPGA. If they generate a sine with the DAC NCO in another frequency will come out a wave composed with another .. Is there any setting possible to make the NCO to "fit" the signals or can only double the frequency of the input through it?

I attached a print to illustrate the "wave composed with another"

In this case, the first sine is 62.5Mhz via an NCO running at 250Mhz in the FPGA (4 samples) and adding 31.25Mhz with a sine generated by the internal DAC NCO running at 500Mhz ..

The pure sine (without use of the DAC NCO) with 4 samples coming from the FPGA and 4x interp IN DAC(16 samples).

Thanks a lot and have a great week!

Att,

Juliano K. Cioffi - FAE 

Latinrep South America - Analog Devices

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  • 0
    •  Analog Employees 
    on Mar 7, 2016 9:08 PM

    If you are using the internal DAC PLL and you are not getting a lock indication, then the part's output can not be expected to be accurate.  When using the DAC PLL, the REFCLKP/N pins should be supplied with the reference clock (seems like 500MHz from your case), not the DACCLKP/N pins - can you confirm you're sending the appropriate reference clock frequency signal to the right pins when using the DAC PLL?  Perhaps you can probe the clock signal to confirm it's at the correct frequency as well.  The clock source (either to the DACCLK or REFCLK pins) to the AD9125 must be source-synchronous or frequency locked to the clock going to the FPGA if you're not using the AD9516 to generate the clock to the DAC and FPGA (are you using the Analog Devices DPG pattern generator or some other pattern generator?).  Once the clock signals going to the part (DACCLK or REFCLK and the DCI data clock input from the FPGA) are confirmed that they are at the correct frequencies for the data interface configuration you're using (which are you using, dual word mode? word mode? byte mode?) then we can move to confirming the SPI GUI is being set properly for the desired configuration.  Please refer to the datasheet ("CMOS Input Data Ports" section) for information about how the clock setup should be for the DCI and data depending on the input data configuration you choose.

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  • 0
    •  Analog Employees 
    on Mar 7, 2016 9:08 PM

    If you are using the internal DAC PLL and you are not getting a lock indication, then the part's output can not be expected to be accurate.  When using the DAC PLL, the REFCLKP/N pins should be supplied with the reference clock (seems like 500MHz from your case), not the DACCLKP/N pins - can you confirm you're sending the appropriate reference clock frequency signal to the right pins when using the DAC PLL?  Perhaps you can probe the clock signal to confirm it's at the correct frequency as well.  The clock source (either to the DACCLK or REFCLK pins) to the AD9125 must be source-synchronous or frequency locked to the clock going to the FPGA if you're not using the AD9516 to generate the clock to the DAC and FPGA (are you using the Analog Devices DPG pattern generator or some other pattern generator?).  Once the clock signals going to the part (DACCLK or REFCLK and the DCI data clock input from the FPGA) are confirmed that they are at the correct frequencies for the data interface configuration you're using (which are you using, dual word mode? word mode? byte mode?) then we can move to confirming the SPI GUI is being set properly for the desired configuration.  Please refer to the datasheet ("CMOS Input Data Ports" section) for information about how the clock setup should be for the DCI and data depending on the input data configuration you choose.

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