AD9125 internal NCO

Hello I have a development running inside a design house and I have been asked for this support:

They are trying to use the internal NCO from the DAC to shift the frequency of the input sine wave.

With that  it would be possible inject a sine to 7.8125Mhz in DAC(32 samples with the interface / NCO of the FPGA to 250Mhz), to have more samples per full wave, and increase its output frequency with the internal DAC NCO.

However, they can only configure the internal NCO with the same frequency of the input coming from the FPGA. If they generate a sine with the DAC NCO in another frequency will come out a wave composed with another .. Is there any setting possible to make the NCO to "fit" the signals or can only double the frequency of the input through it?

I attached a print to illustrate the "wave composed with another"

In this case, the first sine is 62.5Mhz via an NCO running at 250Mhz in the FPGA (4 samples) and adding 31.25Mhz with a sine generated by the internal DAC NCO running at 500Mhz ..

The pure sine (without use of the DAC NCO) with 4 samples coming from the FPGA and 4x interp IN DAC(16 samples).

Thanks a lot and have a great week!

Att,

Juliano K. Cioffi - FAE 

Latinrep South America - Analog Devices

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  • Hi,

    Thank you very much for you help Larry.

    At what sampling rate are you running the AD9125 DAC?

    The DAC is running at 1GHz. We are using the AD9125-EBZ Evaluation Board. The CLKIN port is being fed by an 500Mhz/1.8V/LVDS coming from an external PLL which is also feeding my FPGA(250Mhz in phase). The AD9516 on the EBZ is disabled so the 500Mhz clock is passing through to the AD9125. The AD9125's internal PLL is multiplying this clock by to to achieve the 1GHZ to match the x4 interpolation factor.

    What is the frequency of the AD9125 output signal you want to generate and is it a tone?

    I was expecting to generate a 93.75Mhz(31.25 + 62.5) sine wave.

    Use of the NCO requires use of an I/Q pair of signals. The sampling rate of the FPGA is the DAC sampling rate divided by the interpolation factor.

    I'm using I as the positive and Q as the negative part signal at 250Mhz. The DAC is interpolating x4 the 250Mhz to match the 1Ghz DACCLK frequency and the "IQ Pairs" is activated on AD9125/AD9122 GUI.

    I'm pretty sure it's a clock problem. But I couldn't put my fingers on it yet.

    Another thing that is disturbing me is that I've never seen the DAC's PLL lock signal go active. Although the same weird sine composition happen if I do not use the DAC's PLL and run it straight on the 500Mhz clock or from the AD9516 generating a 500Mhz DAC Clk and a Ref Clk at any division rate with AD9516's "PLL Lock" signal active.

    Another information that may be relevant is, when I use the AD9125's clock multiplier or the on board AD9516 PLL, my sinusoidal signal come out with a little shift in frequency. For example, if I'm working at 250Mhz on all clocks and I'm generating a theoretical 31,25Mhz sine, my actual sine DAC output is perfectly at 31,25Mhz. Now, if I upsample that by 2 and activate the clock multiplier to generate a 500Mhz DAC clk, my output sine wave is at 30.0Mhz. I tough this could be related to the upsampler, so I did the opposite, I got a 250Mhz rate on DCI clk, fed the DAC with 125Mhz, and used the clock multiplier to match the 250Mhz, and got the same 30,0Mhz output without upsampling. I'm not sure if this is abnormal or not, we can easily workaround this with our low grain external PLL. But this might be related to the NCO composite wave issue we are having.

    Thank you very much!

    Cheers.

Reply
  • Hi,

    Thank you very much for you help Larry.

    At what sampling rate are you running the AD9125 DAC?

    The DAC is running at 1GHz. We are using the AD9125-EBZ Evaluation Board. The CLKIN port is being fed by an 500Mhz/1.8V/LVDS coming from an external PLL which is also feeding my FPGA(250Mhz in phase). The AD9516 on the EBZ is disabled so the 500Mhz clock is passing through to the AD9125. The AD9125's internal PLL is multiplying this clock by to to achieve the 1GHZ to match the x4 interpolation factor.

    What is the frequency of the AD9125 output signal you want to generate and is it a tone?

    I was expecting to generate a 93.75Mhz(31.25 + 62.5) sine wave.

    Use of the NCO requires use of an I/Q pair of signals. The sampling rate of the FPGA is the DAC sampling rate divided by the interpolation factor.

    I'm using I as the positive and Q as the negative part signal at 250Mhz. The DAC is interpolating x4 the 250Mhz to match the 1Ghz DACCLK frequency and the "IQ Pairs" is activated on AD9125/AD9122 GUI.

    I'm pretty sure it's a clock problem. But I couldn't put my fingers on it yet.

    Another thing that is disturbing me is that I've never seen the DAC's PLL lock signal go active. Although the same weird sine composition happen if I do not use the DAC's PLL and run it straight on the 500Mhz clock or from the AD9516 generating a 500Mhz DAC Clk and a Ref Clk at any division rate with AD9516's "PLL Lock" signal active.

    Another information that may be relevant is, when I use the AD9125's clock multiplier or the on board AD9516 PLL, my sinusoidal signal come out with a little shift in frequency. For example, if I'm working at 250Mhz on all clocks and I'm generating a theoretical 31,25Mhz sine, my actual sine DAC output is perfectly at 31,25Mhz. Now, if I upsample that by 2 and activate the clock multiplier to generate a 500Mhz DAC clk, my output sine wave is at 30.0Mhz. I tough this could be related to the upsampler, so I did the opposite, I got a 250Mhz rate on DCI clk, fed the DAC with 125Mhz, and used the clock multiplier to match the 250Mhz, and got the same 30,0Mhz output without upsampling. I'm not sure if this is abnormal or not, we can easily workaround this with our low grain external PLL. But this might be related to the NCO composite wave issue we are having.

    Thank you very much!

    Cheers.

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