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# AD9106 Sawtooth frequency range as function of CLK

Today I've had a real long look at the datasheet, trying to figure out the lowest sawtooth frequency possible given a certain clock frequency CLK. This information is critical to see if I need two separate IC's or if I can do with a single AD9106.

From the four lines on page 27 (Rev. A), I assume that the sawtooth generator runs at CLK and you can divide the clock up to 64x by means of SAW_STEPx field, thus each sawtooth step would take 64/CLK seconds. To calculate the sawtooth frequency, I guess I would need to know the number of steps, i.e. the number of bits of the sawtooth waveform counter?

Let's say that CLK = 180MHz, the sawtooth generator has 12 bits (i.e. 4096 steps) and the SAW_STEP register is 63, the lowest sawtooth frequency would be (180MHz/63)/4096 = 697.5Hz, correct? Can anyone confirm the number of steps for a full sawtooth waveform?

I do realise that one can lower the frequency by choosing a lower CLK frequency, the question comes down to 'what is the biggest difference in frequency between the DDS sine wave and sawtooth waveform?'

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• I know I am re-opening this thread after a long time passed, but I needed clarification about AD9106 and I share the result.

It is clear that the SAW generator internally has 2^14 steps, so frequency is actually 1/4 of what is expected by simply dividing the clock by the number of "expected" steps, where expected is 2^12 being the AD9106 specified as a 12 bit DAC.

But what about the output steps from SAW generator? From the block diagram in the datasheet, I should expect that these 14 internal bits are right-shifted twice and the output waveform has a 12-bit resolution, being the output DAC a 12-bit device.

From some first measures, I was not able to see the steps, too small for an 8-bit scope. But after re-arranging the testbed, I got a step amplitude in agreement with my guess of an actual 12-bit output resolution based on the datasheet block diagram.

Enrico

• Hello Enrico,