AD9144

AD9144

 

I am trying to set up the AD9144 DAC registers but there are some questions that I would like answered and I was hoping that someone in the community has had previous experience with the AD9144 DAC registers.

 

I will list the questions that I have.

 

Two questions that I have that are not part of the registers are:

 

  1. Is the input signal pins 5 and 6, SYSREF±, supposed to be at the same frequency as the input signal pins 2 and 3, CLK±? My clock oscillator is 2.8GHz.
  2. Can anyone tell me what I am supposed to utilize the SYNCOUT0+ and SYNCOUT0−, pins 23 and 24 for?

 

These questions have to deal with the registers.

 

I do not need all of the differential SERDIN inputs.  I only need one differential SERDIN input.

I also want to utilize a three wire interface.

 

Here are the registers I know I have to set up.

 

Register

0x000

0x12D

0x146

0x201

0x232

0x2A4

0x333

 

I feel that I am missing some registers that I need to set up.

 

Can anyone tell me what registers I need or do not need to set up the AD9144 DAC for my needs?

  • 0
    •  Analog Employees 
    on Sep 12, 2016 9:29 PM

    The SYSREF+/- signal is a system reference clock signal only needed if you wish to use Subclass 1 to achieve deterministic latency at the DAC output.  It can be sent in a one-shot pulse or a continuous signal.  This clock is meant to be running at low speed and just be a system reference clock for synchronization purposes.  The clock you're providing to the CLK+/- pins is either the direct DAC clock rate (which looks like you're sending since it's a high frequency at the maximum DAC rate) or a reference clock for the on-chip PLL if you don't wish to generate/provide the full high-frequency DAC clock rate.

    The SYNCOUT+/- pins are signals that are sent from the DAC to the FPGA/ASIC that is driving the SERDES data to the DAC.  These are used a signals between the two parts as to the status of the SERDES link establishment and are sent from the DAC automatically based on whether the DAC is ready to perform synchronization and they remain high if the link status is good.  The SYSREF and SYNCOUT signals are all defined as part of the JESD204B SERDES specification so I would recommend familiarizing yourself with the standard spec to find out more information on the protocol itself. There is also a collection of articles into a 'Survival Guide' by some applications engineers about the JESD204B protocol that would likely be helpful that can be found here: http://www.analog.com/media/en/technical-documentation/technical-articles/JESD204B-Survival-Guide.pdf.

    As for what to program in the DAC, for a quick overview of the modes and features available on the part and how to actually go about programming the part (there are several register writes that are necessary to program for this part in order to set it up in a particular configuration) please refer to the "Device Setup Guide" section found in the datasheet. It is written as a 'worksheet' of sorts where it shows variables in some registers and how to calculate them to determine what to program for different mode configurations.  The different mode options are also listed in that section for reference.  As long as the lane rate and DAC sampling rate for a given mode configuration stay within the specified limits in the datasheet then the mode can be used for that part.